{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T14:47:48Z","timestamp":1761662868593},"reference-count":15,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2011,9,1]],"date-time":"2011-09-01T00:00:00Z","timestamp":1314835200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,9]]},"DOI":"10.1109\/tvlsi.2010.2053395","type":"journal-article","created":{"date-parts":[[2010,7,19]],"date-time":"2010-07-19T19:49:52Z","timestamp":1279568992000},"page":"1718-1722","source":"Crossref","is-referenced-by-count":27,"title":["A 3.57 Gb\/s\/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology"],"prefix":"10.1109","volume":"19","author":[{"given":"Won-Joo","family":"Yun","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hyun-Woo","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dongsuk","family":"Shin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Suki","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.641693"},{"key":"ref11","first-page":"282","article-title":"A 0.1-to-1.5 GHz 4.2 mW all-digital DLL with dual duty-cycle correction circuit and update gear circuit for DRAM in 66 nm CMOS technology","author":"yun","year":"2008","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref12","first-page":"285","article-title":"A low jitter, fast recoverable, fully analog DLL using tracking ADC for high speed and low stand-by power DDR I\/O interface","author":"kim","year":"2003","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2006.357920"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.908002"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.916623"},{"key":"ref4","first-page":"283","article-title":"A low cost high performance register-controlled digital DLL for 1 Gbps x32 DDR SDRAM","author":"kwak","year":"2003","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.800922"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2000.852847"},{"key":"ref5","first-page":"160","article-title":"A 2.5 Gb\/s\/pin 256 Mb GDDR3 SDRAM with series pipelined CAS latency control and dual-loop DLL","author":"lee","year":"2006","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref8","first-page":"287","article-title":"Built-in duty cycle corrector using coded phase blending scheme for DDR\/DDR2 synchronous DRAM application","author":"kim","year":"2003","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.760373"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.826820"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542317"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.835809"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5961802\/05504196.pdf?arnumber=5504196","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:47:13Z","timestamp":1633913233000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5504196\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,9]]},"references-count":15,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2053395","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,9]]}}}