{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T06:12:08Z","timestamp":1747807928295},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2011,10,1]],"date-time":"2011-10-01T00:00:00Z","timestamp":1317427200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,10]]},"DOI":"10.1109\/tvlsi.2010.2057520","type":"journal-article","created":{"date-parts":[[2010,8,10]],"date-time":"2010-08-10T19:29:39Z","timestamp":1281468579000},"page":"1931-1935","source":"Crossref","is-referenced-by-count":31,"title":["Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power\/Performance Tradeoffs"],"prefix":"10.1109","volume":"19","author":[{"given":"Mostafa E.","family":"Salehi","sequence":"first","affiliation":[]},{"given":"Mehrzad","family":"Samadi","sequence":"additional","affiliation":[]},{"given":"Mehrdad","family":"Najibi","sequence":"additional","affiliation":[]},{"given":"Ali","family":"Afzali-Kusha","sequence":"additional","affiliation":[]},{"given":"Masoud","family":"Pedram","sequence":"additional","affiliation":[]},{"given":"Sied Mehdi","family":"Fakhraie","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1109\/TCAD.2005.853703","article-title":"Optimal intratask dynamic Voltage-Scaling technique and its practical extensions","volume":"25","author":"seo","year":"2006","journal-title":"IEEE Trans Comput -Aided Des Integr Circuits Syst"},{"key":"ref11","first-page":"456","article-title":"Procrastinating voltage scheduling with discrete frequency sets","author":"lu","year":"2006","journal-title":"Proc Des Autom Test Euro"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.250"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1023\/A:1011132221066"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.896909"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2019803"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.838021"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283790"},{"key":"ref18","doi-asserted-by":"crossref","DOI":"10.1007\/978-0-387-71713-5","author":"rabaey","year":"2009","journal-title":"Low Power Design Essentials"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1024393.1024423"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2000.839787"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.839485(410) 24"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269261"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803941"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TII.2006.890494"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2004.35"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870912"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484692"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.833602"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2005309"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/268806.268810"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320116"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2009.07.001"},{"key":"ref23","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref26","author":"hennessy","year":"2005","journal-title":"Computer Organization and Design The Hardware\/Software Interface"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"421","DOI":"10.1016\/j.sysarc.2009.09.001","article-title":"Analysis of network processing workloads","volume":"55","author":"ramaswamy","year":"2009","journal-title":"J Syst Arch"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5978256\/05545490.pdf?arnumber=5545490","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:46:46Z","timestamp":1633913206000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5545490\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":26,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2057520","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,10]]}}}