{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,19]],"date-time":"2025-04-19T04:49:59Z","timestamp":1745038199968},"reference-count":16,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2011,10,1]],"date-time":"2011-10-01T00:00:00Z","timestamp":1317427200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,10]]},"DOI":"10.1109\/tvlsi.2010.2058872","type":"journal-article","created":{"date-parts":[[2010,8,18]],"date-time":"2010-08-18T19:46:10Z","timestamp":1282160770000},"page":"1898-1902","source":"Crossref","is-referenced-by-count":25,"title":["A Novel Programmable Parallel CRC Circuit"],"prefix":"10.1109","volume":"19","author":[{"given":"Martin","family":"Grymel","sequence":"first","affiliation":[]},{"given":"Steve B.","family":"Furber","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.882213"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2008.5074742"},{"key":"ref12","author":"tanenbaum","year":"2003","journal-title":"Computer Networks"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2002.1028931"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2004.1311885"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ACSD.2009.17"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2008741"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/26.141415"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/40.7773"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1234528"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/40.60527"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/54.922807"},{"key":"ref7","first-page":"445","article-title":"A systematic approach for parallel CRC computations","volume":"17","author":"shieh","year":"2001","journal-title":"J Inf Sci Eng"},{"key":"ref2","author":"lin","year":"1983","journal-title":"Error Control Coding"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JRPROC.1961.287814"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"156","DOI":"10.1007\/3-540-61730-2_16","article-title":"Parallel CRC computation in FPGAs","author":"braun","year":"1996","journal-title":"Proc 6th Int Workshop Field-Program Logic Smart Appl New Paradigms Compilers (FPL)"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/5978256\/05549980.pdf?arnumber=5549980","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:44:07Z","timestamp":1633913047000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5549980\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":16,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2058872","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,10]]}}}