{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,24]],"date-time":"2025-03-24T07:09:09Z","timestamp":1742800149354},"reference-count":9,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2011,11,1]],"date-time":"2011-11-01T00:00:00Z","timestamp":1320105600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,11]]},"DOI":"10.1109\/tvlsi.2010.2064793","type":"journal-article","created":{"date-parts":[[2010,9,7]],"date-time":"2010-09-07T20:20:38Z","timestamp":1283890838000},"page":"2135-2139","source":"Crossref","is-referenced-by-count":5,"title":["Security Evaluation of Balanced 1-of-$n$ Circuits"],"prefix":"10.1109","volume":"19","author":[{"given":"Frank","family":"Burns","sequence":"first","affiliation":[]},{"given":"Alex","family":"Bystrov","sequence":"additional","affiliation":[]},{"given":"Albert","family":"Koelmans","sequence":"additional","affiliation":[]},{"given":"Alex","family":"Yakovlev","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1693233"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"58","DOI":"10.1109\/DATE.2005.44","article-title":"A VLSI design flow for secure side-channel attack resistant IC's","author":"tiri","year":"2005","journal-title":"Proc Des Autom Test Eur (DATE)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.61"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2002.1000311"},{"key":"ref8","article-title":"Generalized correlation power analysis","author":"aumnier","year":"2007","journal-title":"Ecrypt Workshop Tools for Cryptanalysis"},{"key":"ref7","year":"2007","journal-title":"Cryptographic Processing and Processors"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"16","DOI":"10.1007\/978-3-540-28632-5_2","article-title":"Correlation power analysis with a leakage model","author":"brier","year":"2004","journal-title":"Proc Cryptograph Hardw Embed Syst (CHES 2004 LCNS 3156)"},{"key":"ref9","author":"burns","year":"2010","journal-title":"Design and security evaluation of balanced 1-of-n circuits"},{"key":"ref1","first-page":"388","article-title":"Differential power analysis","author":"kocher","year":"1999","journal-title":"Proc Adv Cryptography (CRYPTO)"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6017244\/05560768.pdf?arnumber=5560768","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:45:27Z","timestamp":1633913127000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5560768\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,11]]},"references-count":9,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2064793","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,11]]}}}