{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T14:48:27Z","timestamp":1761662907217},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2011,11,1]],"date-time":"2011-11-01T00:00:00Z","timestamp":1320105600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,11]]},"DOI":"10.1109\/tvlsi.2010.2071890","type":"journal-article","created":{"date-parts":[[2010,10,1]],"date-time":"2010-10-01T19:03:08Z","timestamp":1285959788000},"page":"2120-2125","source":"Crossref","is-referenced-by-count":20,"title":["Minimum Supply Voltage and Yield Estimation for Large SRAMs Under Parametric Variations"],"prefix":"10.1109","volume":"19","author":[{"given":"Jiajing","family":"Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Benton H.","family":"Calhoun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.873215"},{"key":"ref11","author":"hesterberg","year":"1988","journal-title":"Advances in importance sampling"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/49.585771"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630041"},{"key":"ref4","first-page":"400","article-title":"Statistical modeling for the minimum standby supply voltage of a full SRAM array","author":"wang","year":"2007","journal-title":"Proc ESSCIRC"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364490"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280733"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469239"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1393921.1393954"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001941"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2008.4681834"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2006.229167"},{"key":"ref9","first-page":"42","article-title":"Large-scale read\/write margin measurement in 45 nm CMOS SRAM arrays","author":"guo","year":"2008","journal-title":"Proc Symp VLSI Circuits"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6017244\/05590277.pdf?arnumber=5590277","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:45:06Z","timestamp":1633913106000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5590277\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,11]]},"references-count":13,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2071890","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,11]]}}}