{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:02:16Z","timestamp":1759147336791},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2011,12,1]],"date-time":"2011-12-01T00:00:00Z","timestamp":1322697600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,12]]},"DOI":"10.1109\/tvlsi.2010.2073489","type":"journal-article","created":{"date-parts":[[2010,10,5]],"date-time":"2010-10-05T20:50:02Z","timestamp":1286311802000},"page":"2184-2194","source":"Crossref","is-referenced-by-count":9,"title":["A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories"],"prefix":"10.1109","volume":"19","author":[{"given":"Chin-Lung","family":"Su","sequence":"first","affiliation":[]},{"given":"Rei-Fu","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Cheng-Wen","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Kun-Lun","family":"Luo","sequence":"additional","affiliation":[]},{"given":"Wen-Ching","family":"Wu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","first-page":"468","article-title":"Error catch and analysis for semiconductor memories using March tests","author":"wu","year":"2000","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Des (ICCAD)"},{"key":"ref32","author":"van de goor","year":"1998","journal-title":"Testing Semiconductor Memories Theory and Practice"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271092"},{"key":"ref30","first-page":"256","article-title":"Defect oriented fault analysis for SRAM","author":"huang","year":"2003","journal-title":"Proc 12th IEEE Asian Test Symp (ATS)"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990265"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2002.1029766"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1992.276223"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2002.1017700"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1023\/A:1016557927479"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041777"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1198687"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894250"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1989.56835"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743312"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270863"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253672"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159742"},{"key":"ref28","first-page":"175","article-title":"Defect analysis system speeds test and repair of redundant memories","volume":"57","author":"tarr","year":"1984","journal-title":"Electron"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"637","DOI":"10.1023\/A:1020805224219","article-title":"A built-in self-test and self-diagnosis scheme for embedded SRAM","volume":"18","author":"wang","year":"2002","journal-title":"J Electron Test Theory Appl"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1049\/el:20083611"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/54.211525"},{"key":"ref6","first-page":"292","article-title":"Enabling embedded memory diagnosis via test response compression","author":"chen","year":"2001","journal-title":"Proc IEEE VLSI Test Symp (VTS)"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/54.922801"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ETW.2000.873789"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.1998.655853"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966641"},{"key":"ref2","author":"wang","year":"2006","journal-title":"Design for Testability VLSI Test Principles and Architectures"},{"key":"ref9","first-page":"384","article-title":"Error detecting refreshment for embedded DRAMs","author":"hellebrand","year":"1999","journal-title":"Proc IEEE VLSI Test Symp (VTS)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/54.748806"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2005988"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DBT.2004.1408968"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/24.994929"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2000.887170"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2004.43"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821925"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JRPROC.1952.273898"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6059694\/05593911.pdf?arnumber=5593911","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:46:06Z","timestamp":1633913166000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5593911\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12]]},"references-count":36,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2073489","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,12]]}}}