{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T05:53:18Z","timestamp":1775454798619,"version":"3.50.1"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2011,12,1]],"date-time":"2011-12-01T00:00:00Z","timestamp":1322697600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2011,12]]},"DOI":"10.1109\/tvlsi.2010.2079339","type":"journal-article","created":{"date-parts":[[2010,11,5]],"date-time":"2010-11-05T19:09:56Z","timestamp":1288984196000},"page":"2229-2242","source":"Crossref","is-referenced-by-count":17,"title":["An Analytical Model Relating FPGA Architecture to Logic Density and Depth"],"prefix":"10.1109","volume":"19","author":[{"given":"Joydip","family":"Das","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrew","family":"Lam","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven J. E.","family":"Wilton","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philip H. W.","family":"Leong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wayne","family":"Luk","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1981.1084958"},{"key":"ref11","first-page":"viii","article-title":"Closing the gap between FPGAs and ASICs, keynote address","author":"rose","year":"2006","journal-title":"Proc Int Conf FPT"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/43.251146"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1971.223159"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/639929.639936"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1979.1084635"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-8499-9"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.850868"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508156"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.900744"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311187"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2009.5377647"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1344671.1344694"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2008.4629935"},{"key":"ref7","first-page":"96","article-title":"An analytical FPGA delay path model","author":"hung","year":"2009","journal-title":"Proc Int Conf FPT"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272315"},{"key":"ref1","first-page":"135","article-title":"Improving FPGA performance and area using an adaptive logic module","author":"hutton","year":"2004","journal-title":"Proc Int Conf FPL"},{"key":"ref20","first-page":"370","article-title":"Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations","author":"gao","year":"2005","journal-title":"Proc Int Symp QED"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/503057.503058"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"ref24","author":"yang","year":"1991","journal-title":"Logic Synthesis and Optimization Benchmarks User Guide Version 3 0"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/333032.333040"},{"key":"ref25","year":"0","journal-title":"Quartus II University Interface Program (QUIP)"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6059694\/05608539.pdf?arnumber=5608539","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,11]],"date-time":"2021-10-11T00:45:54Z","timestamp":1633913154000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5608539\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12]]},"references-count":25,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2079339","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,12]]}}}