{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,3,2]],"date-time":"2024-03-02T18:58:51Z","timestamp":1709405931244},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2012,3,1]],"date-time":"2012-03-01T00:00:00Z","timestamp":1330560000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2012,3]]},"DOI":"10.1109\/tvlsi.2010.2102056","type":"journal-article","created":{"date-parts":[[2011,1,28]],"date-time":"2011-01-28T19:47:21Z","timestamp":1296244041000},"page":"410-423","source":"Crossref","is-referenced-by-count":5,"title":["Test Pattern Generation of Relaxed $n$-Detect Test Sets"],"prefix":"10.1109","volume":"20","author":[{"given":"Stelios N.","family":"Neophytou","sequence":"first","affiliation":[]},{"given":"Maria K.","family":"Michael","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","author":"bushnell","year":"2000","journal-title":"Essentials of Electronic Testing"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.62"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/12.663775"},{"key":"ref36","doi-asserted-by":"crossref","first-page":"539","DOI":"10.1145\/1278480.1278617","article-title":"new test data decompressor for low power applications","author":"mrugalski","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref35","first-page":"450","article-title":"Defect aware test patterns","author":"tang","year":"2005","journal-title":"Proc DATE"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1974.224020"},{"key":"ref10","first-page":"380","article-title":"Delay test generation with all reachable output propagation and multiple excitation proc","author":"vaidya","year":"2005","journal-title":"Proc DFT"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2006.125"},{"key":"ref12","first-page":"445","article-title":"On n-detect pattern set optimization","author":"huang","year":"2006","journal-title":"Proc ISQED"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2007.24"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687418"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.177"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1023\/A:1012872706123"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1995.479997"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894274"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.833617"},{"key":"ref28","author":"lee","year":"1993","journal-title":"Atalanta An efficient ATPG for combinational circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894222"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.47"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271091"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2004.1299221"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.805726"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1230800.1230810"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437649"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966652"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/54.902820"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2005.85"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114938"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090833"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456928"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386971"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.822103"},{"key":"ref23","first-page":"53","article-title":"An efficient test relaxation technique for combinational &#38;amp; full-scan sequential circuits","author":"el-maleh","year":"2002","journal-title":"Proc VTS"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.178"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2008.4479845"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6151946\/05704232.pdf?arnumber=5704232","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:46:50Z","timestamp":1633909610000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5704232\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,3]]},"references-count":36,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2010.2102056","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,3]]}}}