{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T18:52:12Z","timestamp":1771613532567,"version":"3.50.1"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2012,4,1]],"date-time":"2012-04-01T00:00:00Z","timestamp":1333238400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2012,4]]},"DOI":"10.1109\/tvlsi.2011.2109068","type":"journal-article","created":{"date-parts":[[2011,2,24]],"date-time":"2011-02-24T20:44:13Z","timestamp":1298580253000},"page":"697-710","source":"Crossref","is-referenced-by-count":13,"title":["VLSI Architecture of Arithmetic Coder Used in SPIHT"],"prefix":"10.1109","volume":"20","author":[{"given":"Kai","family":"Liu","sequence":"first","affiliation":[]},{"given":"Evgeniy","family":"Belyaev","sequence":"additional","affiliation":[]},{"given":"Jie","family":"Guo","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1147\/rd.426.0753"},{"key":"ref32","doi-asserted-by":"crossref","first-page":"643","DOI":"10.1007\/3-540-44687-7_71","article-title":"FPGA-Based modelling unit for high speed lossless arithmetic coding","volume":"2147 2001","author":"stefo","year":"2001","journal-title":"Field-Program Logic Appl Lecture Notes Comput Sci"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2004.08.013"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2006.11.009"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/DCC.1993.253137"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/81.703836"},{"key":"ref10","first-page":"1034","article-title":"A pipeline chip for quasi arithmetic coding","volume":"e84 a","author":"wiseman","year":"2001","journal-title":"IEICE Trans Fundamentals"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2000.901112"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1117\/1.2952851"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.advengsoft.2008.08.004"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1134\/S1064226908060065"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2000.859236"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"452","DOI":"10.1109\/ICIP.1995.537669","article-title":"A fast and area-efficient VLSI architecture for embedded image coding","volume":"3","author":"bac","year":"1995","journal-title":"Proc Int Conf Image Process"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ADFSP.1998.685718"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2005.852625"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1093\/ietfec\/e89-a.12.3613"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2006.875171"},{"key":"ref4","year":"2000","journal-title":"JPEG2000 Part I Final Draft International Standard"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008144820747"},{"key":"ref3","year":"1993","journal-title":"ISO\/IEC JTC1 Information Technology-Digital Compression and Coding of Continuous-Tone Still Images-Part 1 Requirements and Guidelines"},{"key":"ref6","first-page":"714","article-title":"VLSI architecture of MQ encoder in JPEG2000","volume":"31","author":"cao","year":"2004","journal-title":"J Xidian Xuebao"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1155\/2009\/479281"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/83.847830"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2003.815173"},{"key":"ref7","year":"2003","journal-title":"Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec H 264 ISO\/IEC 14496-10 AVC)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1147\/rd.232.0149"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/76.499834"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.203.0198"},{"key":"ref20","author":"ritter","year":"2002","journal-title":"Wavelet based image compression using FPGAs"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DCC.2000.838201"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1016\/j.image.2008.01.004"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/83.826776"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/214762.214771"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1023\/A:1022123829466"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/92.273153"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6168597\/05720281.pdf?arnumber=5720281","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:52:46Z","timestamp":1633909966000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5720281\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,4]]},"references-count":35,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2011.2109068","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,4]]}}}