{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T17:53:23Z","timestamp":1774720403449,"version":"3.50.1"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2012,5,1]],"date-time":"2012-05-01T00:00:00Z","timestamp":1335830400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2012,5]]},"DOI":"10.1109\/tvlsi.2011.2116814","type":"journal-article","created":{"date-parts":[[2011,3,17]],"date-time":"2011-03-17T20:05:27Z","timestamp":1300392327000},"page":"902-910","source":"Crossref","is-referenced-by-count":34,"title":["System-Wide Leakage-Aware Energy Minimization Using Dynamic Voltage Scaling and Cache Reconfiguration in Multitasking Systems"],"prefix":"10.1109","volume":"20","author":[{"family":"Weixun Wang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Mishra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","first-page":"105","article-title":"Scheduling techniques for reducing leakage power in hard real-time systems","author":"lee","year":"2003","journal-title":"Proc 15th Euromicro Conf Real-Time Syst"},{"key":"ref32","first-page":"95","article-title":"Dynamic and aggressive scheduling techniques for power-aware real-time systems","author":"aydin","year":"2001","journal-title":"Proc Real-Time Syst Symp"},{"key":"ref31","first-page":"3","article-title":"Mibench: A free, commercially representative embedded benchmark suite","author":"guthaus","year":"2001","journal-title":"Proc IEEE Int Workshop Workload Characterization"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1997.645830"},{"key":"ref34","year":"2000","journal-title":"The Embedded Microprocessor Benchmark Consortium"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2003.1250885"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"1376","DOI":"10.1109\/TVLSI.2005.862718","article-title":"Bus encoding for total power reduction using a leakage-aware buffer configuration","volume":"13","author":"rao","year":"2005","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref12","year":"2008","journal-title":"CACTI 5 3"},{"key":"ref13","first-page":"275","article-title":"Leakage aware dynamic voltage scaling for real-time embedded systems","author":"jejurikar","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269096"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855964"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283828"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"78","DOI":"10.1145\/1013235.1013261","article-title":"Dynamic Voltage Scaling for Systemwide Energy Minimization in Real-Time Embedded Systems","author":"jejurikar","year":"2004","journal-title":"Proceedings of the 2004 International Symposium on Low Power Electronics and Design LPE"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2006.320167"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1134650.1134673"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.39"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2009.66"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/HSC.1999.777411"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"241","DOI":"10.1145\/344166.344610","article-title":"a low power unified cache architecture providing power and performance flexibility","author":"malik","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"},{"key":"ref6","author":"buttazzo","year":"1995","journal-title":"Hard Real-Time Computing Systems"},{"key":"ref29","author":"burger","year":"1996","journal-title":"Evaluating future microprocessors The Simplescalar tool set"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2009.22"},{"key":"ref8","first-page":"42","article-title":"Transistor elements for 30 nm physical gate lengths and beyond","volume":"6","author":"doyle","year":"2002","journal-title":"Intel Technol J"},{"key":"ref7","author":"liu","year":"2000","journal-title":"Real-Time Systems"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/43.811318"},{"key":"ref9","first-page":"141","article-title":"Subthreshold leakage modeling and reduction techniques","author":"kao","year":"2002","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Des (ICCAD)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1016720.1016777"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837452"},{"key":"ref22","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1109\/LPE.2000.155259","article-title":"gated-v\/sub dd\/: a circuit technique to reduce leakage in deep-submicron cache memories","author":"powell","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"},{"key":"ref21","first-page":"234","article-title":"A self-tuning configurable cache","author":"gordon-ross","year":"2007","journal-title":"Proc Des Autom Conf"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.4"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/1289881.1289924"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2010.22"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1067915.1067921"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6178142\/05734888.pdf?arnumber=5734888","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,20]],"date-time":"2021-11-20T12:44:21Z","timestamp":1637412261000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5734888\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5]]},"references-count":34,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2011.2116814","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,5]]}}}