{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T14:49:27Z","timestamp":1761662967388},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2012,5,1]],"date-time":"2012-05-01T00:00:00Z","timestamp":1335830400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2012,5]]},"DOI":"10.1109\/tvlsi.2011.2129602","type":"journal-article","created":{"date-parts":[[2011,4,8]],"date-time":"2011-04-08T20:21:11Z","timestamp":1302294071000},"page":"969-973","source":"Crossref","is-referenced-by-count":19,"title":["A Spur Suppression Technique Using an Edge-Interpolator for a Charge-Pump PLL"],"prefix":"10.1109","volume":"20","author":[{"family":"Jaehyouk Choi","sequence":"first","affiliation":[]},{"family":"Woonyun Kim","sequence":"additional","affiliation":[]},{"family":"Kyutae Lim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2005716"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/PACRIM.1991.160827"},{"key":"ref12","first-page":"2432","article-title":"A spur suppression technique for phase-locked frequency synthesizers","author":"lee","year":"2006","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref13","first-page":"395","article-title":"A ring VCO with wide and linear tuning characteristics for a cognitive radio system","author":"choi","year":"2008","journal-title":"RFIC Symp Dig Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1998.695039"},{"key":"ref3","author":"banerjee","year":"2006","journal-title":"PLL Performance Simulation and Design"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2002.802965"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.817601"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.858322"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.807169"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1997.606653"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1999.780807"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.880030"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6178142\/05744146.pdf?arnumber=5744146","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:47:55Z","timestamp":1633909675000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5744146\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5]]},"references-count":13,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2011.2129602","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,5]]}}}