{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:07:55Z","timestamp":1758892075413},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2012,8,1]],"date-time":"2012-08-01T00:00:00Z","timestamp":1343779200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2012,8]]},"DOI":"10.1109\/tvlsi.2011.2159633","type":"journal-article","created":{"date-parts":[[2011,7,21]],"date-time":"2011-07-21T14:44:02Z","timestamp":1311259442000},"page":"1373-1382","source":"Crossref","is-referenced-by-count":6,"title":["Jitter Analysis of Polyphase Filter-Based Multiphase Clock in Frequency Multiplier"],"prefix":"10.1109","volume":"20","author":[{"family":"Jee Khoi Yin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P. K.","family":"Chan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"1579","DOI":"10.1109\/TVLSI.2008.2005522","article-title":"A DLL design for testing I\/O setup and hold times","volume":"17","author":"jia","year":"2009","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref11","first-page":"396","article-title":"A low-jitter skew-calibrated multi-phase clock generator for time-interleaved applications","author":"wu","year":"2001","journal-title":"Proc Int Solid-State Circuits Conf"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.821773"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.874036"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.904155"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.925664"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2008477"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.921571"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2002.806248"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"27","DOI":"10.1109\/ISCAS.1994.409188","article-title":"Analysis of timing jitter in CMOS ring oscillators","author":"weigandt","year":"1994","journal-title":"Proc Int Symp Circuits Syst (ISCAS)"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"1414","DOI":"10.1109\/JSSC.2002.803936","article-title":"A low-power small-area <formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\pm}7.28$<\/tex><\/formula>-ps-jitter 1-GHz DLL-based clock generator","volume":"37","author":"kim","year":"2002","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.890315"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.880609"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.837997"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2087992"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2019757"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914287"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.792603"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"2483","DOI":"10.1109\/TCSI.2008.920088","article-title":"A multiphase-output delay-locked loop with a novel start-controlled phase\/frequency detector","volume":"55","author":"chang","year":"2008","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref20","first-page":"415","article-title":"A sub-psec jitter PLL for clock generation in 0.12 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu$<\/tex> <\/formula>m digital CMOS","author":"da dalt","year":"2002","journal-title":"Proc European Solid-State Circuits Conference"},{"key":"ref22","author":"kundert","year":"2006","journal-title":"Predicting the phase noise and jitter of PLL-based frequency synthesizers"},{"key":"ref21","author":"chien","year":"2000","journal-title":"Low-noise local oscillator design techniques using a DLL-based frequency multiplier for wireless applications"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/4.760373"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2000.852702"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6218240\/05955093.pdf?arnumber=5955093","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:53:29Z","timestamp":1642006409000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5955093\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,8]]},"references-count":24,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2011.2159633","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,8]]}}}