{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,10]],"date-time":"2025-05-10T06:03:33Z","timestamp":1746857013707},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2012,9,1]],"date-time":"2012-09-01T00:00:00Z","timestamp":1346457600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2012,9]]},"DOI":"10.1109\/tvlsi.2011.2160410","type":"journal-article","created":{"date-parts":[[2011,8,3]],"date-time":"2011-08-03T21:19:57Z","timestamp":1312406397000},"page":"1621-1633","source":"Crossref","is-referenced-by-count":18,"title":["Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint"],"prefix":"10.1109","volume":"20","author":[{"family":"Li Jiang","sequence":"first","affiliation":[]},{"family":"Qiang Xu","sequence":"additional","affiliation":[]},{"given":"K.","family":"Chakrabarty","sequence":"additional","affiliation":[]},{"given":"T. M.","family":"Mak","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/944027.944029"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1023\/A:1014916913577"},{"key":"ref32","first-page":"416","article-title":"Wrapper design for testing IP cores with multiple clock domains","author":"xu","year":"2004","journal-title":"Proc Design Automat Test Europe"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271102"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817128"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2007.53"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2009.4796577"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253695"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/980152.980157"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045019"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1252857"},{"key":"ref13","first-page":"100","article-title":"Using a distributed rectangle bin-packing approach for core-based SoC test scheduling with power constraints","author":"xia","year":"2003","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Des"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2004.60"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041747"},{"key":"ref16","first-page":"552","article-title":"Thermal-aware test scheduling and hot spot temperature minimization for core-based systems","author":"liu","year":"2005","journal-title":"Proc IEEE Int Symp Defect Fault Tolerance VLSI Syst"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.252"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.873898"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-007-5030-6"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.888266"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.59"},{"key":"ref27","year":"2009","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1148015.1148016"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSM.2007.4446880"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.125"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.45.3030"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355573"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.125"},{"key":"ref2","year":"0","journal-title":"Yole development Market trends for 3-D stacking"},{"key":"ref9","first-page":"220","article-title":"Test architecture design and optimization for three-dimensional SoCs","author":"jiang","year":"2009","journal-title":"Proc Design Automat Test Europe"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"ref20","author":"mak","year":"2008","journal-title":"Testing of 3-D Circuites"},{"key":"ref22","first-page":"208","article-title":"Scan chain design for three-dimensional integrated circuits (3D ICs)","author":"wu","year":"2007","journal-title":"Proc Int Conf Comput Des"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2007.4437621"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2008.4751864"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469556"},{"key":"ref26","first-page":"191","article-title":"Layout-driven test-architecture design and optimization for 3-D SoCs under pre-bond test-pin-count constraint","author":"jiang","year":"2009","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Des"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ETSYM.2010.5512787"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6236332\/05963754.pdf?arnumber=5963754","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:53:03Z","timestamp":1642006383000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5963754\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,9]]},"references-count":38,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2011.2160410","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,9]]}}}