{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T06:05:40Z","timestamp":1648879540025},"reference-count":8,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2012,10,1]],"date-time":"2012-10-01T00:00:00Z","timestamp":1349049600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2012,10]]},"DOI":"10.1109\/tvlsi.2011.2163533","type":"journal-article","created":{"date-parts":[[2011,9,22]],"date-time":"2011-09-22T18:28:39Z","timestamp":1316716119000},"page":"1885-1890","source":"Crossref","is-referenced-by-count":0,"title":["Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating"],"prefix":"10.1109","volume":"20","author":[{"given":"Nam Sung","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abhishek","family":"Sinkar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jun","family":"Seomun","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Youngsoo","family":"Shin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","year":"2010","journal-title":"Synopsys power-gating design methodology based on SMIC 90 nm process"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2005.1554483"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722282"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1535\/itj.0904.02"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TSM.2007.913186"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594263"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146943"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996588"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6246737\/06019046.pdf?arnumber=6019046","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:48:13Z","timestamp":1633909693000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6019046\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,10]]},"references-count":8,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2011.2163533","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,10]]}}}