{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T06:46:03Z","timestamp":1648709163668},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2012,10,1]],"date-time":"2012-10-01T00:00:00Z","timestamp":1349049600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2012,10]]},"DOI":"10.1109\/tvlsi.2011.2166092","type":"journal-article","created":{"date-parts":[[2011,12,3]],"date-time":"2011-12-03T16:55:01Z","timestamp":1322931301000},"page":"1818-1827","source":"Crossref","is-referenced-by-count":6,"title":["An All-Digital Clock Synchronization Buffer With One Cycle Dynamic Synchronizing"],"prefix":"10.1109","volume":"20","author":[{"given":"Kuo-Hsing","family":"Cheng","sequence":"first","affiliation":[]},{"given":"Kai-Wei","family":"Hong","sequence":"additional","affiliation":[]},{"given":"Chi-Fa","family":"Hsu","sequence":"additional","affiliation":[]},{"given":"Bo-Qian","family":"Jiang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"671","article-title":"Low power clock generator based on an area-reduced interleaved synchronous mirror delay scheme","author":"sung","year":"2002","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/4.748189"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.753681"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.835816"},{"key":"ref14","first-page":"283","article-title":"Arbitrary duty cycle synchronous mirror delay circuits design","author":"cheng","year":"2006","journal-title":"Proc IEEE Asian Solid-State Circuits Conf"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2049387"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.827800"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1049\/el:20080622"},{"key":"ref18","year":"2009","journal-title":"HSPICE User Guide Analyzing Electrical Yields"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2024804"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2046235"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.889381"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2047994"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2007.4425736"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1996.542310"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.910798"},{"key":"ref2","first-page":"82","article-title":"A 0.17&#x2013;1.4 GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme","author":"shin","year":"2008","journal-title":"Proc Euro Solid-State Circuits Conf"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2016993"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.1997.623831"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2003.1257082"},{"key":"ref21","doi-asserted-by":"crossref","first-page":"1461","DOI":"10.1109\/TVLSI.2008.2004591","article-title":"A low-jitter open-loop all-digital clock generator with two-cycle lock-time","volume":"17","author":"kim","year":"2009","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6246737\/06093716.pdf?arnumber=6093716","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:47:11Z","timestamp":1633909631000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6093716\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,10]]},"references-count":21,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2011.2166092","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,10]]}}}