{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,12,31]],"date-time":"2022-12-31T07:11:36Z","timestamp":1672470696481},"reference-count":23,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2012,11,1]],"date-time":"2012-11-01T00:00:00Z","timestamp":1351728000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2012,11]]},"DOI":"10.1109\/tvlsi.2011.2166416","type":"journal-article","created":{"date-parts":[[2011,10,12]],"date-time":"2011-10-12T19:22:30Z","timestamp":1318447350000},"page":"1997-2010","source":"Crossref","is-referenced-by-count":6,"title":["Formal-Analysis-Based Trace Computation for Post-Silicon Debug"],"prefix":"10.1109","volume":"20","author":[{"given":"Marcel","family":"Gort","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Flavio M.","family":"De Paula","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Johnny J. W.","family":"Kuan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tor M.","family":"Aamodt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alan J.","family":"Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven J. E.","family":"Wilton","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jin","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2008.41"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1464520"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2006.238683"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2189395"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.51"},{"key":"ref15","doi-asserted-by":"crossref","first-page":"285","DOI":"10.1109\/TCAD.2008.2009158","article-title":"Algorithms for state restoration and trace- signal selection for data acquisition in silicon debug","volume":"28","author":"ko","year":"2009","journal-title":"IEEE Trans Comput -Aided Des Integr Circuits"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146917"},{"key":"ref17","first-page":"1","article-title":"Using magellan to diagnose post- silicon bugs","volume":"4","author":"ahlschlager","year":"2004","journal-title":"Synopsys Verification Avenue Tech Bull"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/FAMCAD.2007.26"},{"key":"ref19","first-page":"111","article-title":"The chip is ready, am I done? on-chip verification using assertion processors","author":"nacif","year":"2003","journal-title":"Proc Int Conf Very Large Scale Integr System-on-Chip (VLSI-SoC)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966662"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/54.706037"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805821"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ETSYM.2004.1347600"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.896905"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.157"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MTV.2008.22"},{"key":"ref1","first-page":"35","article-title":"Backspace: Formal analysis for post-silicon debug","author":"de paula","year":"2008","journal-title":"Formal Meth Comput -Aided Design"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2023198"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159685"},{"key":"ref22","article-title":"Programmable logic core based post-silicon debug for SOCs","author":"quinton","year":"2007","journal-title":"4th IEEE Silicon Debug Diagnosis Workshop"},{"key":"ref21","first-page":"294","article-title":"Adding debug enhancements to assertion checkers for hardware emulation and silicon debug","author":"boul","year":"2006","journal-title":"Proc Int Conf Comput Design"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770739"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6252108\/06041051.pdf?arnumber=6041051","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:47:08Z","timestamp":1633909628000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6041051\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11]]},"references-count":23,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2011.2166416","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,11]]}}}