{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,6,27]],"date-time":"2023-06-27T06:51:48Z","timestamp":1687848708419},"reference-count":17,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2012,11,1]],"date-time":"2012-11-01T00:00:00Z","timestamp":1351728000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2012,11]]},"DOI":"10.1109\/tvlsi.2011.2168432","type":"journal-article","created":{"date-parts":[[2011,10,12]],"date-time":"2011-10-12T19:22:30Z","timestamp":1318447350000},"page":"2138-2142","source":"Crossref","is-referenced-by-count":4,"title":["Non-Uniform Coverage by $n$-Detection Test Sets"],"prefix":"10.1109","volume":"20","author":[{"given":"Irith","family":"Pomeranz","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2006.125"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147186"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1230800.1230810"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894196"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966689"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20060120"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355762"},{"key":"ref17","article-title":"Defect-based tests: A key enabler for successful migration to structural test","author":"sengupta","year":"1999","journal-title":"Intel Technol J"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743151"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/43.644620"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/43.833205"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766675"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"23","DOI":"10.1109\/VTEST.2004.1299221","article-title":"An experimental study of <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$n$<\/tex><\/formula>-detect scan ATPG patterns on a processor","author":"venkataraman","year":"2004","journal-title":"Proc VLSI Test Symp"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271091"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1995.529895"},{"key":"ref1","first-page":"91","article-title":"Quantifying non-target defect detection by target fault test sets","author":"butler","year":"1991","journal-title":"Proc European Test Conf"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"450","DOI":"10.1109\/DATE.2005.110","article-title":"Defect aware test patterns","author":"tang","year":"2005","journal-title":"Proc Conf Design Automation Test Eur"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6252108\/06036209.pdf?arnumber=6036209","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:47:26Z","timestamp":1633909646000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6036209\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,11]]},"references-count":17,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2011.2168432","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,11]]}}}