{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:02:10Z","timestamp":1761580930429},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2012,12,1]],"date-time":"2012-12-01T00:00:00Z","timestamp":1354320000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2012,12]]},"DOI":"10.1109\/tvlsi.2011.2170228","type":"journal-article","created":{"date-parts":[[2011,10,31]],"date-time":"2011-10-31T14:27:33Z","timestamp":1320071253000},"page":"2265-2277","source":"Crossref","is-referenced-by-count":5,"title":["Semi-Serial On-Chip Link Implementation for Energy Efficiency and High Throughput"],"prefix":"10.1109","volume":"20","author":[{"given":"Ethiopia","family":"Nigussie","sequence":"first","affiliation":[]},{"given":"Sampo","family":"Tuuna","sequence":"additional","affiliation":[]},{"given":"Juha","family":"Plosila","sequence":"additional","affiliation":[]},{"given":"Jouni","family":"Isoaho","sequence":"additional","affiliation":[]},{"given":"H.","family":"Tenhunen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910807"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/HOTI.2009.13"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/22.310584"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/4.68134"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.837987"},{"key":"ref30","first-page":"315","article-title":"Differential current-mode signaling for robust and power efficient on-chip global interconnects","author":"zhang","year":"2005","journal-title":"Proc 14th IEEE Electrical Performance of Electronic Packag"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.812366"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.812509"},{"key":"ref35","author":"lee","year":"2001","journal-title":"An Efficient I\/O and Clcok Recovery for TERABIT Integrated Circuits Design"},{"key":"ref34","author":"djordjevic","year":"1999","journal-title":"Software and Users Manual Version 2 0"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014206"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373470"},{"key":"ref11","author":"dally","year":"2003","journal-title":"Principles and Practices of Interconnection Networks"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2007.4341515"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.29"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243841"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1183401.1183430"},{"key":"ref16","article-title":"Keynote Lecture: Spidergon STNoC: The Communication Infrastructure for Multiprocessor Architectures","author":"coppola","year":"0","journal-title":"Int Forum Appl -Specific Multiprocessor SoC"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878263"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.902209"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357970"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378787"},{"key":"ref27","first-page":"6","article-title":"Analysis of pulse signaling for low-power on-chip global bus design","author":"chen","year":"2006","journal-title":"Proc IEEE Int Symp Quality Electron Design"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523070"},{"key":"ref6","year":"2007","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.857351"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910957"},{"key":"ref8","author":"benini","year":"2006","journal-title":"Networks on Chips Technology and Tools"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966750"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378783"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.164"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2013772"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1353610.1353620"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2005.1469344"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2005.1469345"},{"key":"ref42","first-page":"182","article-title":"High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90 nm CMOS","author":"seo","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf Dig Techn Papers"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9781139166980"},{"key":"ref41","first-page":"66","article-title":"A 4 Gb\/s\/ch 356 fJ\/b 10 mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90 nm CMOS","author":"kim","year":"2009","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2007.20"},{"key":"ref44","first-page":"265","article-title":"A 32 Gb\/s on-chip bus with driver pre-emphasis signaling","author":"zhang","year":"2006","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.826196"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2020859"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6257480\/06062666.pdf?arnumber=6062666","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:47:24Z","timestamp":1633909644000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6062666\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,12]]},"references-count":44,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2011.2170228","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,12]]}}}