{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,12,31]],"date-time":"2022-12-31T09:18:37Z","timestamp":1672478317025},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2012,12,1]],"date-time":"2012-12-01T00:00:00Z","timestamp":1354320000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2012,12]]},"DOI":"10.1109\/tvlsi.2011.2173220","type":"journal-article","created":{"date-parts":[[2011,11,17]],"date-time":"2011-11-17T20:47:18Z","timestamp":1321562838000},"page":"2333-2337","source":"Crossref","is-referenced-by-count":10,"title":["Analyzing the Impact of Joint Optimization of Cell Size, Redundancy, and ECC on Low-Voltage SRAM Array Total Area"],"prefix":"10.1109","volume":"20","author":[{"given":"Nam Sung","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stark C.","family":"Draper","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shi-Ting","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sumeet","family":"Katariya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hamid Reza","family":"Ghasemi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Taejoon","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/4.499733"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0390"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1993744.1993755"},{"key":"ref13","author":"rao","year":"1989","journal-title":"Error-control coding for computer systems"},{"key":"ref14","first-page":"351","article-title":"Parichute: Generalized turbocode-based error correction for near-threshold caches","author":"miller","year":"2007","journal-title":"Proc Int Symp Microarch (MICRO)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1978.1051122"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2011972"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647605"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1979.19370"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.22"},{"key":"ref7","year":"2009","journal-title":"ITRS"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2007.4342739"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDER.2004.1356522"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/4.75047"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6257480\/06081976.pdf?arnumber=6081976","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:53:14Z","timestamp":1633909994000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6081976\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,12]]},"references-count":14,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2011.2173220","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,12]]}}}