{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T00:28:14Z","timestamp":1761611294282},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2013,1]]},"DOI":"10.1109\/tvlsi.2011.2180548","type":"journal-article","created":{"date-parts":[[2012,1,17]],"date-time":"2012-01-17T20:36:16Z","timestamp":1326832576000},"page":"78-91","source":"Crossref","is-referenced-by-count":18,"title":["Formal Verification of Architectural Power Intent"],"prefix":"10.1109","volume":"21","author":[{"given":"Aritra","family":"Hazra","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sahil","family":"Goyal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pallab","family":"Dasgupta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ajit","family":"Pal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref31","year":"2008","journal-title":"UPF-2 0 Unified Power Format 2 0 Standard [Draft Version]IEEE Draft Standard for Design and Verification of Low Power Integrated Circuits"},{"key":"ref30","year":"0","journal-title":"A Power-Performance Analysis Simulator From IBM"},{"key":"ref10","first-page":"3","article-title":"Upping verification productivity of low power designs","author":"chidolue","year":"2008","journal-title":"Proc DVCON"},{"key":"ref11","first-page":"288","article-title":"Functional verification of low power designs at RTL","author":"crone","year":"2007","journal-title":"Workshop for Power Tim Model Opt Simulation (PATMOS) LNCS-4644"},{"key":"ref12","article-title":"Design for power gating&#x2014;and what UPF can, and cannot, do for you!","author":"flynn","year":"2009","journal-title":"SNUG"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837469"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2004.1349303"},{"key":"ref15","year":"2006","journal-title":"IEEE VHDL Standard"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.8"},{"key":"ref17","author":"jadcherla","year":"2009","journal-title":"Verification Methodology Manual for Low Power (VMM-LP)"},{"key":"ref18","author":"keating","year":"2008","journal-title":"Low Power Methodology Manual (LPMM)For System-on-Chip Design"},{"key":"ref19","first-page":"53","article-title":"Power assertions and coverage for improving quality of low power verification and closure of power intent","author":"khan","year":"2008","journal-title":"Proc DVCON"},{"key":"ref28","year":"0","journal-title":"Early Power Estimation Tool From Atrenta"},{"key":"ref4","author":"bailey","year":"2007","journal-title":"Low Power Design and Verification Techniques"},{"key":"ref27","author":"snyder","year":"2008","journal-title":"Formal Verification Checks IC Power Reduction Features"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-73625-7_31"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2355-0"},{"key":"ref29","year":"2004","journal-title":"SystemVerilog LRM 3 1a by Accellera"},{"key":"ref5","first-page":"11","article-title":"To retain or not to retain: How do I verify the state elements of my low power design?","author":"bailey","year":"2008","journal-title":"Proc DVCON"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1147\/rd.475.0653"},{"key":"ref7","first-page":"228","article-title":"Low power verification methodology using UPF","author":"bembaron","year":"2009","journal-title":"Proc DVCON"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.102"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2325-3"},{"key":"ref1","year":"0","journal-title":"Advanced Configuration and Power Interface"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2009.5185383"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2009.5012137"},{"key":"ref21","year":"0","journal-title":"An Industrial Formal Verification Tool from Synopsys"},{"key":"ref24","first-page":"42","article-title":"Static and formal verification of power aware designs at the RTL using UPF","author":"mukherjee","year":"2008","journal-title":"Proc DVCON"},{"key":"ref23","first-page":"262","article-title":"Enhanced LEON3 low power IP core for DSM technologies","author":"marcinek","year":"2009","journal-title":"Proc 14th Int Conf Mixed Design Integr Circuits Syst (MIXDES'07)"},{"key":"ref26","author":"roy","year":"2000","journal-title":"Low-Power CMOS VLSI Circuit Design"},{"key":"ref25","year":"2008","journal-title":"A Practical Guide for Low Power DesignAn Experience With CPF"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6387661\/06133315.pdf?arnumber=6133315","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,10,10]],"date-time":"2021-10-10T23:51:45Z","timestamp":1633909905000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6133315\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,1]]},"references-count":31,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2011.2180548","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,1]]}}}