{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,25]],"date-time":"2026-07-25T13:41:13Z","timestamp":1784986873289,"version":"3.55.0"},"reference-count":10,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2013,2,1]],"date-time":"2013-02-01T00:00:00Z","timestamp":1359676800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2013,2]]},"DOI":"10.1109\/tvlsi.2012.2186990","type":"journal-article","created":{"date-parts":[[2012,3,6]],"date-time":"2012-03-06T01:05:32Z","timestamp":1330995932000},"page":"250-258","source":"Crossref","is-referenced-by-count":11,"title":["A Wide-Range PLL Using Self-Healing Prescaler\/VCO in 65-nm CMOS"],"prefix":"10.1109","volume":"21","author":[{"given":"I-Ting","family":"Lee","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yun-Ta","family":"Tsai","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shen-Iuan","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.997856"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/4.918909"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977477"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818298"},{"key":"ref5","first-page":"272","article-title":"A 1 V CMOS PLL designed in high-leakage CMOS process operating at 10&#x2013;700 MHz","author":"holzer","year":"2002","journal-title":"Proc IEEE Int Solid-State Circuits Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/4.823449"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.720406"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2008.930154"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1093\/ietele\/e89-c.3.295"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"1687","DOI":"10.1109\/JPROC.2009.2024663","article-title":"Analog circuit design in nanoscale CMOS technologies","volume":"18","author":"lewyn","year":"2009","journal-title":"Proc IEEE"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6414677\/06164303.pdf?arnumber=6164303","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:56:13Z","timestamp":1638219373000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6164303\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,2]]},"references-count":10,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2012.2186990","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,2]]}}}