{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,4]],"date-time":"2024-07-04T10:39:16Z","timestamp":1720089556258},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2013,3,1]],"date-time":"2013-03-01T00:00:00Z","timestamp":1362096000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2013,3]]},"DOI":"10.1109\/tvlsi.2012.2187224","type":"journal-article","created":{"date-parts":[[2012,3,8]],"date-time":"2012-03-08T19:12:43Z","timestamp":1331233963000},"page":"566-570","source":"Crossref","is-referenced-by-count":16,"title":["A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology"],"prefix":"10.1109","volume":"21","author":[{"given":"Sebastian","family":"Hoppner","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Holger","family":"Eisenreich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stephan","family":"Henker","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dennis","family":"Walter","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georg","family":"Ellguth","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ren\u00e9","family":"Schuffny","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref31","doi-asserted-by":"crossref","first-page":"117","DOI":"10.1109\/TCSII.2008.2010189","article-title":"Jitter analysis and a benchmarking figure-of-merit for phase-locked loops","volume":"56","author":"gao","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref30","first-page":"431","article-title":"A wide tuning range (1 GHz-to-15 Ghz) fractional-N all-digital PLL in 45 nm SOI","author":"rylyakov","year":"2008","journal-title":"Proc Custom Integr Circuits Conf"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2008.4538747"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878271"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"1067","DOI":"10.1109\/TCSII.2007.906943","article-title":"A flying-adder on-chip frequency generator for complex SoC environment","volume":"54","author":"xiu","year":"2007","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910966"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.840089"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2008.12.005"},{"key":"ref16","author":"mcneill","year":"2009","journal-title":"The Designer's Guide to Jitter in Ring Oscillators"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.918077"},{"key":"ref18","author":"shu","year":"2005","journal-title":"CMOS PLL Synthesizers Analysis and Design"},{"key":"ref19","first-page":"264","article-title":"An open-loop clock generator for fast frequency scaling in 65 nm CMOS technology","author":"hppner","year":"2011","journal-title":"Proc Int Conf Mixed Design Integr Circuits Syst"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2074950"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2008.4681893"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2009.0097"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2011.05.003"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001947"},{"key":"ref29","first-page":"478","article-title":"A 1.4 PSRMS-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65 nm CMOS","author":"grollitsch","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers (ISSCC)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910957"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2013772"},{"key":"ref7","first-page":"123","article-title":"System level analysis of fast, per-core DVFS using on-chip switching regulators","author":"kim","year":"2008","journal-title":"Proc IEEE 14th Int Symp High Perform Comput Arch (HPCA)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001949"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SMICND.2008.4703435"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2007.362"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2002.806248"},{"key":"ref22","year":"2010","journal-title":"JESD79-3E DDR3 SDRAM Specification"},{"key":"ref21","year":"2009","journal-title":"JESD79-2F DDR2 SDRAM Specification"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042250"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2157259"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2010.2056013"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"525","DOI":"10.1109\/TCSII.2009.2020948","article-title":"A leakage-compensated PLL in 65-nm CMOS technology","volume":"56","author":"hung","year":"2009","journal-title":"IEEE Trans Circuits Syst II Exp Briefs"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6466554\/06166353.pdf?arnumber=6166353","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:56:13Z","timestamp":1638219373000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6166353\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,3]]},"references-count":31,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2012.2187224","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,3]]}}}