{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,30]],"date-time":"2025-10-30T07:02:48Z","timestamp":1761807768137},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2013,6,1]],"date-time":"2013-06-01T00:00:00Z","timestamp":1370044800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2013,6]]},"DOI":"10.1109\/tvlsi.2012.2202700","type":"journal-article","created":{"date-parts":[[2012,7,24]],"date-time":"2012-07-24T18:11:06Z","timestamp":1343153466000},"page":"1094-1102","source":"Crossref","is-referenced-by-count":55,"title":["Data Allocation Optimization for Hybrid Scratch Pad Memory With SRAM and Nonvolatile Memory"],"prefix":"10.1109","volume":"21","author":[{"given":"Jingtong","family":"Hu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chun Jason","family":"Xue","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qingfeng","family":"Zhuge","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei-Che","family":"Tseng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Edwin H.-M.","family":"Sha","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ESTIMedia.2011.6088521"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024819"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2039370.2039420"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2097307"},{"key":"ref36","first-page":"3","article-title":"MiBench: A free, commercially representative embedded benchmark suite","author":"guthaus","year":"2001","journal-title":"Proc Int Workshop Workload Character"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687449"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722171"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2012.120"},{"key":"ref11","first-page":"9-1","article-title":"Write activity reduction on non-volatile main memories for embedded chip multi-processors","volume":"12","author":"hu","year":"2012","journal-title":"ACM Trans Embedded Comput Syst"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1785481.1785503"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSISOC.2010.5642609"},{"key":"ref14","first-page":"737","article-title":"Power and performance of read-write aware hybrid caches with non-volatile memories","author":"wu","year":"2009","journal-title":"Proc Design Autom Test Eur Conf"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1366110.1366204"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"554","DOI":"10.1145\/1391469.1391610","article-title":"Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement","author":"dong","year":"2008","journal-title":"Proc 40th Annu Conf Design Automation"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555761"},{"key":"ref18","first-page":"136","article-title":"Energy- and endurance-aware design of phase change memory caches","author":"joo","year":"2010","journal-title":"Proc Design Autom Test Eur Conf"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1151074.1151085"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837363"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1143\/JJAP.44.2691"},{"key":"ref27","first-page":"7","article-title":"Minimizing write activities to non-volatile memory via scheduling and recomputation","author":"hu","year":"2010","journal-title":"Proc 8th IEEE Symp Appl Specific Process"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609379"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555758"},{"key":"ref29","first-page":"136","article-title":"Toward energy efficient hybrid on-chip scratch pad memory with non-volatile memory","author":"hu","year":"2011","journal-title":"Proc Design Autom Test Eur Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555759"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2012.6288188"},{"key":"ref7","first-page":"119","article-title":"A 0.9 V, 65 nm logic-compatible embedded DRAM with <formula formulatype=\"inline\"><tex Notation=\"TeX\">${&#x003E;}{\\rm 1}~{\\rm ms}$<\/tex><\/formula> data retention time and 53% less static power than a power-gated SRAM","author":"chun","year":"2009","journal-title":"Proc ACM Int Symp Low Power Electronics and Design"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382555"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/INTERACT.2012.6339622"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CODES.2002.1003604"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2001.156226"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/951746.951747"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.822123"},{"key":"ref24","first-page":"148","article-title":"A nondestructive self-reference scheme for spin-transfer torque random access memory (STT-RAM)","author":"chen","year":"2010","journal-title":"Proc Design Autom Test Eur Conf"},{"key":"ref23","first-page":"521","article-title":"Heap data allocation to scratch-pad memory in embedded systems","volume":"1","author":"dominguez","year":"2005","journal-title":"J Embedded Comput"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456923"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6517540\/06248275.pdf?arnumber=6248275","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,22]],"date-time":"2022-01-22T21:56:49Z","timestamp":1642888609000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6248275\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,6]]},"references-count":36,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2012.2202700","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,6]]}}}