{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,8]],"date-time":"2025-12-08T22:13:35Z","timestamp":1765232015069},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2013,6,1]],"date-time":"2013-06-01T00:00:00Z","timestamp":1370044800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2013,6]]},"DOI":"10.1109\/tvlsi.2012.2203326","type":"journal-article","created":{"date-parts":[[2012,7,13]],"date-time":"2012-07-13T11:58:48Z","timestamp":1342180728000},"page":"1041-1052","source":"Crossref","is-referenced-by-count":4,"title":["Dual-Level Adaptive Supply Voltage System for Variation Resilience"],"prefix":"10.1109","volume":"21","author":[{"given":"Kyu-Nam","family":"Shim","sequence":"first","affiliation":[]},{"given":"Jiang","family":"Hu","sequence":"additional","affiliation":[]},{"given":"Jose","family":"Silva-Martinez","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.110"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2007.66"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2008.4479792"},{"key":"ref12","first-page":"191","article-title":"Revival: A variation-tolerant architecture using voltage interpolation and variable latency","author":"liang","year":"2008","journal-title":"Proc IEEE Int Symp Comput Arch"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/82.673644"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.842831"},{"key":"ref15","first-page":"1","article-title":"Low drop-out linear regulators: Design considerations and trends for high power supply rejection (PSR)","author":"sanchez-sinencio","year":"2010","journal-title":"Proc IEEE Santa Clara Valley Solid State Circuits Soc"},{"key":"ref16","first-page":"123","article-title":"System level analysis of fast, per-core DVFS using on-chip switching regulators","author":"kim","year":"2008","journal-title":"Proc IEEE Int Symp High Perform Comput Arch"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2009.5325937"},{"key":"ref18","first-page":"504","article-title":"Mitigating the impact of process variations on processor register files and execution units","author":"liang","year":"2006","journal-title":"Proc MICRO"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250703"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852459"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817120"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2004.1349331"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.844305"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803949"},{"key":"ref29","year":"2008","journal-title":"Predictive Technology Model"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810053"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/871506.871537"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893626"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167534"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.110"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2004.1349358"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.22"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1974.1050532"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1971.1050151"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"155","DOI":"10.1145\/1391469.1391511","article-title":"application-driven floorplan-aware voltage island design","author":"sengupta","year":"2008","journal-title":"2008 45th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766651"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6517540\/06238381.pdf?arnumber=6238381","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:56:15Z","timestamp":1638219375000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6238381\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,6]]},"references-count":30,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2012.2203326","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,6]]}}}