{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,24]],"date-time":"2025-04-24T04:32:48Z","timestamp":1745469168331,"version":"3.40.4"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2013,7,1]],"date-time":"2013-07-01T00:00:00Z","timestamp":1372636800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2013,7,1]],"date-time":"2013-07-01T00:00:00Z","timestamp":1372636800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2013,7,1]],"date-time":"2013-07-01T00:00:00Z","timestamp":1372636800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2013,7]]},"DOI":"10.1109\/tvlsi.2012.2210450","type":"journal-article","created":{"date-parts":[[2012,8,28]],"date-time":"2012-08-28T18:20:16Z","timestamp":1346178016000},"page":"1189-1200","source":"Crossref","is-referenced-by-count":0,"title":["Impact of III\u2013V and Ge Devices on Circuit Performance"],"prefix":"10.1109","volume":"21","author":[{"given":"Jeongha","family":"Park","sequence":"first","affiliation":[{"name":"Stanford University, Stanford, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Saeroonter","family":"Oh","sequence":"additional","affiliation":[{"name":"LG Display, Research and Development Center, Paju, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"SoYoung","family":"Kim","sequence":"additional","affiliation":[{"name":"College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"H.-S. Philip","family":"Wong","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S. Simon","family":"Wong","sequence":"additional","affiliation":[{"name":"Stanford University, Stanford, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696326"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2002.801433"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.824300"},{"journal-title":"Power Consumption in 65 Nm FPGA","year":"2007","author":"curd","key":"ref32"},{"key":"ref31","doi-asserted-by":"crossref","first-page":"135","DOI":"10.1561\/1000000005","volume":"2","author":"kuon","year":"2008","journal-title":"Foundations and Trends in Electronic Design Automation"},{"key":"ref30","doi-asserted-by":"crossref","first-page":"188","DOI":"10.1145\/313817.313920","article-title":"The design of a low energy FPGA","author":"george","year":"1999","journal-title":"Proceedings 1999 International Symposium on Low Power Electronics and Design (Cat No 99TH8477) LPE"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2019279"},{"journal-title":"Stratix iii Programmable Power","year":"2007","key":"ref36"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2006.243746"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/4.62145"},{"journal-title":"Modeling of IIIV nanoscale field-effect transistors for logic circuits","year":"2010","author":"oh","key":"ref10"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"2546","DOI":"10.1109\/TED.2008.2002994","article-title":"Lateral and vertical scaling of <formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\rm In}_{0.7}{\\rm Ga}_{0.3}{\\rm As}$<\/tex><\/formula> HEMTs for post-Si-CMOS logic applications","volume":"55","author":"kim","year":"2008","journal-title":"IEEE Trans Electron Device"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2033411"},{"key":"ref13","first-page":"767","article-title":"Performance evaluation of 50 nm <formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\rm In}_{0.7}{\\rm Ga}_{0.3}{\\rm As}$<\/tex><\/formula> HEMTs for beyond-CMOS logic applications","author":"kim","year":"2005","journal-title":"IEDM Tech Dig"},{"key":"ref14","first-page":"625","article-title":"Heterogeneous integration of enhancement mode <formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\rm In}_{0.7}{\\rm Ga}_{0.3}{\\rm As}$<\/tex><\/formula> quantum well transistor on silicon substrate using thin <formula formulatype=\"inline\"><tex Notation=\"TeX\">$({\\leq}{\\rm 2}~\\mu{\\rm m})$<\/tex><\/formula> composite buffer architecture for high-speed and low-voltage (0.5 V) logic applications","author":"hudait","year":"2007","journal-title":"IEDM Tech Dig"},{"key":"ref15","first-page":"10.6.1","article-title":"High-mobility 0.85 nm-EOT Si0.45Ge0.55-pFETs: Delivering high performance at scaled VDD","author":"mitard","year":"2010","journal-title":"IEEE IEDM Tech Dig"},{"key":"ref16","first-page":"134","article-title":"1 <formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\rm mA}\/\\mu{\\rm m}$<\/tex><\/formula>-ION strained SiGe45%-IFQW pFETs with raised and embedded S\/D","author":"mitard","year":"2011","journal-title":"Proc Symp VLSI Technol"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2053226"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2159870"},{"journal-title":"Predictive Technology Model (PTM)","year":"0","key":"ref19"},{"key":"ref4","first-page":"90","article-title":"Symmetrical 45 nm pMOS on <formula formulatype=\"inline\"><tex Notation=\"TeX\">$[110]$<\/tex><\/formula> substrate with excellent S\/D extension distribution and mobility enhancement","author":"hwang","year":"2004","journal-title":"Symp VLSI Technology Dig Tech Papers"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2007.31"},{"key":"ref3","first-page":"1032","article-title":"<formula formulatype=\"inline\"><tex Notation=\"TeX\">$(110)$<\/tex><\/formula> channel, SiON gate-dielectric pMOS with record high <formula formulatype=\"inline\"><tex Notation=\"TeX\">${\\rm I}_{\\rm on}=1~{\\rm mA}\/\\mu{\\rm m}$<\/tex><\/formula> through channel stress and source drain external resistance <formula formulatype=\"inline\"><tex Notation=\"TeX\">$({\\rm R}_{\\rm ext})$<\/tex><\/formula> engineering","author":"yang","year":"2007","journal-title":"IEEE IEDM Tech Dig"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.1996.547493"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796665"},{"key":"ref5","first-page":"1330","article-title":"Interface-engineered high-mobility high-<formula formulatype=\"inline\"><tex Notation=\"TeX\">$k\/{\\rm Ge}$<\/tex><\/formula> pMOSFETs with 1-nm equivalent oxide thickness","volume":"56","author":"xie","year":"2009","journal-title":"IEEE Trans Electron Devices"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2003.1292037"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2008.4588611"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2008.917817"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424320"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424359"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"1110","DOI":"10.1109\/LED.2010.2063012","article-title":"90 nm self-aligned enhancement-mode InGaAs HEMT for logic applications","volume":"31","author":"doornbos","year":"2010","journal-title":"IEEE Electron Device Lett"},{"key":"ref20","first-page":"229","author":"neamen","year":"2002","journal-title":"Semiconductor Physics and Devices"},{"key":"ref22","first-page":"205","author":"weste","year":"2005","journal-title":"CMOS VLSI Design A Circuits and Systems Perspective"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"2003","key":"ref21"},{"key":"ref24","first-page":"1","article-title":"Logical effort: Designing for speed on the back of an envelope","author":"sutherland","year":"1991","journal-title":"Proc Univ California\/Santa Cruz Conf Adv Res VLSI"},{"key":"ref23","first-page":"179","author":"rabaey","year":"2003","journal-title":"Digital Integrated Circuits A Design Perspective"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052168"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/4.126534"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6545337\/06289382.pdf?arnumber=6289382","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,23]],"date-time":"2025-04-23T17:59:31Z","timestamp":1745431171000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6289382\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,7]]},"references-count":39,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2012.2210450","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2013,7]]}}}