{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,2]],"date-time":"2026-01-02T07:48:04Z","timestamp":1767340084488},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2013,9,1]],"date-time":"2013-09-01T00:00:00Z","timestamp":1377993600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2013,9]]},"DOI":"10.1109\/tvlsi.2012.2214491","type":"journal-article","created":{"date-parts":[[2012,12,19]],"date-time":"2012-12-19T19:41:03Z","timestamp":1355946063000},"page":"1655-1668","source":"Crossref","is-referenced-by-count":20,"title":["RegularRoute: An Efficient Detailed Router Applying Regular Routing Patterns"],"prefix":"10.1109","volume":"21","author":[{"given":"Yanheng","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chris","family":"Chu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907068"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1561\/1000000015"},{"key":"ref11","article-title":"Layout printability verification and physical design regularity: Roadmap enablers for the next decade","author":"capodieci","year":"2006","journal-title":"Proc EDPS"},{"key":"ref12","year":"1998","journal-title":"IBM-PLACE 2 0 Benchmark Suites"},{"key":"ref13","year":"2005","journal-title":"ISPD05 placement contest benchmarks"},{"key":"ref14","year":"2006","journal-title":"ISPD06 placement contest benchmarks"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/505348.505366"},{"key":"ref16","author":"garey","year":"1979","journal-title":"Computers and Intractability A Guide to the Theory of NP-Completeness"},{"key":"ref17","first-page":"283","article-title":"DOPPLER: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing","author":"lin","year":"2011","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160923"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024902"},{"key":"ref28","first-page":"576","article-title":"FastRoute 4.0: Global router with efficient via minimization","author":"xu","year":"2009","journal-title":"Proc Asia South Pacific Design Autom Conf"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/43.920694"},{"key":"ref27","year":"2008","journal-title":"ISPD08 global routing contest benchmarks"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270336"},{"key":"ref6","first-page":"674","article-title":"A new FPGA detailed routing approach via search-based Boolean satisfiability","volume":"21","author":"nam","year":"2006","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref29","first-page":"344","article-title":"FastRoute 3.0: A fast and high quality global router based on virtual capacity","author":"zhang","year":"2008","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.826547"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2013274"},{"key":"ref7","first-page":"59","article-title":"Track assignment: A desirable intermediate step between global routing and detailed routing","author":"batterywala","year":"2002","journal-title":"Proc Int Conf Comput -Aided Design"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1982.1269993"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/800158.805069"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228441"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687465"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228469"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1960397.1960410"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.809660"},{"key":"ref23","year":"2004","journal-title":"IBM-PLACE 2 0 Benchmark Suites"},{"key":"ref26","year":"2007","journal-title":"ISPD07 global routing contest benchmarks"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357975"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6574241\/06387627.pdf?arnumber=6387627","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:54:45Z","timestamp":1638219285000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6387627\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,9]]},"references-count":30,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2012.2214491","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,9]]}}}