{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:57:41Z","timestamp":1759147061073},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2013,10,1]],"date-time":"2013-10-01T00:00:00Z","timestamp":1380585600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2013,10]]},"DOI":"10.1109\/tvlsi.2012.2220868","type":"journal-article","created":{"date-parts":[[2012,10,23]],"date-time":"2012-10-23T18:05:53Z","timestamp":1351015553000},"page":"1915-1927","source":"Crossref","is-referenced-by-count":5,"title":["Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems"],"prefix":"10.1109","volume":"21","author":[{"given":"Sohan S.","family":"Purohit","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sai Rahul","family":"Chalamalasetti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Martin","family":"Margala","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wim A.","family":"Vanderbauwhede","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2009.5377622"},{"key":"ref32","year":"0","journal-title":"Xilinx FPU Documentation"},{"key":"ref31","first-page":"69","article-title":"A new architecture for multiple-precision floating point multiply-add fused unit design","author":"huang","year":"2007","journal-title":"Proc 18th IEEE Symp Comput Arith"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870924"},{"key":"ref35","year":"2001","journal-title":"IEEE754 Floating Point Core"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2003.1227254"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2009.10.002"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2010.02.001"},{"key":"ref12","first-page":"620","article-title":"VLSI design and implementation of low power MAC unit with block enabling technique","volume":"30","author":"shanthala","year":"2009","journal-title":"Eur J Sci Res"},{"key":"ref13","first-page":"24","article-title":"Garp: A MIPS processor with reconfigurable co-processor","author":"hauser","year":"1997","journal-title":"Proc Int Conf FPGA Custom Comput"},{"key":"ref14","first-page":"1","article-title":"Element CXI: Exploring elemental computing in academia","author":"athanas","year":"2009","journal-title":"Proc Int Conf Eng Reconfig Syst Appl"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1964.263830"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2008.01.005"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/92.924037"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.89"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.874302"},{"key":"ref4","year":"2010","journal-title":"DAPDNA-2 Product Brochure"},{"key":"ref28","author":"purohit","year":"2011","journal-title":"Hardware software co-design of a resource efficient coarse grained reconfigurable architecture for high throughput media processing applications"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2010.5540750"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2007.4378781"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2008.4585936"},{"key":"ref29","first-page":"1","article-title":"An ALU cluster with floating point unit for media streaming architecture with homogeneous processor cores","author":"liou","year":"2008","journal-title":"Proc IEEE 13th Asia-Pacific Comput Syst Arch Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2006.883171"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2009.37"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564808"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2008.12.003"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310759"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2009.5272461"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2009.1033"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223648"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1166\/jolpe.2010.1096"},{"key":"ref23","first-page":"45","article-title":"Design-space exploration of energy-delay-area efficient coarse-grain reconfigurable data-path","author":"purohit","year":"2009","journal-title":"Proc IEEE Int Conf VLSI Design"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2009.0099"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2157543"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6594872\/06338360.pdf?arnumber=6338360","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:54:46Z","timestamp":1638219286000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6338360\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,10]]},"references-count":35,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2012.2220868","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,10]]}}}