{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,6]],"date-time":"2025-11-06T12:06:45Z","timestamp":1762430805828},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2013,12,1]],"date-time":"2013-12-01T00:00:00Z","timestamp":1385856000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2013,12]]},"DOI":"10.1109\/tvlsi.2012.2228677","type":"journal-article","created":{"date-parts":[[2013,10,15]],"date-time":"2013-10-15T18:47:42Z","timestamp":1381862862000},"page":"2325-2330","source":"Crossref","is-referenced-by-count":12,"title":["Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform"],"prefix":"10.1109","volume":"21","author":[{"given":"Jun","family":"Han","sequence":"first","affiliation":[]},{"given":"Shuai","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Wei","family":"Huang","sequence":"additional","affiliation":[]},{"given":"Zhiyi","family":"Yu","sequence":"additional","affiliation":[]},{"given":"Xiaoyang","family":"Zeng","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.256"},{"key":"ref3","first-page":"261","article-title":"Montgomery modular multiplication algorithm on multi-core systems","author":"fan","year":"2007","journal-title":"Proc IEEE Workshop Signal Process Syst"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/40.502403"},{"key":"ref10","first-page":"1","article-title":"A low-complexity heterogeneous multi-core platform for security SoC","author":"huang","year":"2010","journal-title":"Proc IEEE Asian Solid-State Circuits Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1228516"},{"key":"ref11","year":"2002","journal-title":"64-Bit Architecture Speeds RSA by 4x"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090680"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CIT.2010.315"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.2307\/2007970"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1049\/ic:20080614"},{"key":"ref9","year":"2009","journal-title":"OSCI TLM-2 0 Language Reference Manual"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6624128\/06409486.pdf?arnumber=6409486","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:54:46Z","timestamp":1638219286000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6409486\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12]]},"references-count":11,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2012.2228677","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,12]]}}}