{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,16]],"date-time":"2026-01-16T06:02:49Z","timestamp":1768543369226,"version":"3.49.0"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2013,12,1]],"date-time":"2013-12-01T00:00:00Z","timestamp":1385856000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2013,12]]},"DOI":"10.1109\/tvlsi.2012.2230655","type":"journal-article","created":{"date-parts":[[2012,12,27]],"date-time":"2012-12-27T19:04:37Z","timestamp":1356635077000},"page":"2334-2338","source":"Crossref","is-referenced-by-count":22,"title":["Concurrent Error Detection for Orthogonal Latin Squares Encoders and Syndrome Computation"],"prefix":"10.1109","volume":"21","author":[{"given":"Pedro","family":"Reviriego","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Salvatore","family":"Pontarelli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Juan Antonio","family":"Maestro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0390"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"30","DOI":"10.1109\/MDT.2011.35","article-title":"Low-power, resilient interconnection with Orthogonal Latin Squares","volume":"28","author":"lee","year":"2011","journal-title":"IEEE Design Test Comput"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2011.3"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.207"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.899241"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1134\/S0032946008020038"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2009.08.007"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821940"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-011-5208-9"},{"key":"ref19","author":"d\ufffdnes","year":"1974","journal-title":"Latin Squares and Their Applications"},{"key":"ref4","first-page":"586","article-title":"DEC ECC design to improve memory reliability in sub-100 nm technologies","author":"naseer","year":"2008","journal-title":"Proc IEEE Int Conf Electron Circuits Syst"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.40"},{"key":"ref6","author":"lin","year":"2004","journal-title":"Error Control Coding"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TAES.2005.1561889"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2009217"},{"key":"ref7","first-page":"1","article-title":"Dynamic low-density parity check codes for fault-tolerant nano-scale memory","author":"ghosh","year":"2007","journal-title":"Foundations of Nanoscience"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1002\/0471792748"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2091432"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.282.0124"},{"key":"ref20","author":"lala","year":"2001","journal-title":"Self-Checking and Fault-Tolerant Digital Design"},{"key":"ref22","first-page":"651","article-title":"Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection","author":"touba","year":"1994","journal-title":"Proc IEEE\/ACM Int Conf Comput -Aided Design"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/92.285745"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/2.56855"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1147\/rd.144.0395"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2007.44"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6624128\/06395842.pdf?arnumber=6395842","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:54:46Z","timestamp":1638219286000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6395842\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12]]},"references-count":25,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2012.2230655","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,12]]}}}