{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:59:50Z","timestamp":1759147190508},"reference-count":48,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2014,1,1]],"date-time":"2014-01-01T00:00:00Z","timestamp":1388534400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,1]]},"DOI":"10.1109\/tvlsi.2012.2233505","type":"journal-article","created":{"date-parts":[[2013,3,21]],"date-time":"2013-03-21T18:02:37Z","timestamp":1363888957000},"page":"13-26","source":"Crossref","is-referenced-by-count":15,"title":["Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches"],"prefix":"10.1109","volume":"22","author":[{"given":"Zhaobo","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xrysovalantis","family":"Kavousianos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yiorgos","family":"Tsiatouhas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1393921.1393942"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2014201"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.894428"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2007.911067"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2110663"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2039761"},{"key":"ref37","doi-asserted-by":"crossref","first-page":"430","DOI":"10.1109\/TVLSI.2006.874378","article-title":"Leakage-suppressed clock-gating circuit with zigzag super cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-v-<formula formulatype=\"inline\"> <tex Notation=\"TeX\">$v_{DD}$<\/tex><\/formula> LSIs","volume":"14","author":"min","year":"2006","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840880"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2169889"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2102054"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.816145"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1013235.1013312"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2004.1349301"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.818127"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012673"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-0391-0"},{"key":"ref15","first-page":"317","article-title":"MTCMOS sequential circuits","author":"kao","year":"2001","journal-title":"Proceedings of the 27th European Solid-State Circuits Conference ESSCIRC"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"495","DOI":"10.1145\/277044.277180","article-title":"MTCMOS hierarchical sizing based on mutual exclusive discharge patterns","author":"kao","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/4.871328"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2001.945394"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/4.400426"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/776028.776032"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2009.5423813"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1464514"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4541731"},{"key":"ref6","first-page":"1","article-title":"Case study of a low power MTCMOS based ARM926 SoC: Design, analysis and test challenges","author":"idgunji","year":"2007","journal-title":"Proc IEEE Int Test Conf"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2041505"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391624"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.821546"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/774572.774601"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.111"},{"key":"ref1","year":"2007","journal-title":"Semiconductor Industry Association"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2006.283888"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/4.585288"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1493989"},{"key":"ref48","author":"lopez","year":"2006","journal-title":"Reuse-Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2003.1231828"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.810785"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIR.2006.307541"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.904101"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2009.4810281"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2010151"},{"key":"ref44","author":"rabaey","year":"2003","journal-title":"Digital Integrated Circuits A Design Perspective"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2008.85"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2035268"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.29"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6690268\/06484194.pdf?arnumber=6484194","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:54:47Z","timestamp":1638219287000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6484194\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,1]]},"references-count":48,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2012.2233505","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,1]]}}}