{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,13]],"date-time":"2024-06-13T02:20:32Z","timestamp":1718245232387},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2014,1,1]],"date-time":"2014-01-01T00:00:00Z","timestamp":1388534400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,1]]},"DOI":"10.1109\/tvlsi.2012.2236690","type":"journal-article","created":{"date-parts":[[2013,6,13]],"date-time":"2013-06-13T18:06:08Z","timestamp":1371146768000},"page":"90-98","source":"Crossref","is-referenced-by-count":8,"title":["Nano Magnetic STT-Logic Partitioning for Optimum Performance"],"prefix":"10.1109","volume":"22","author":[{"given":"Jayita","family":"Das","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Syed M.","family":"Alam","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanjukta","family":"Bhanja","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1063\/1.3314301"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2008.1"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"1688","DOI":"10.1126\/science.1108813","article-title":"Magnetic domain-wall logic","volume":"309","author":"allwood","year":"2005","journal-title":"Science"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2011.2158848"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2005.848129"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1063\/1.1857655"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"2677","DOI":"10.1109\/TMAG.2007.893412","article-title":"The 3-bit gray counter based on magnetic-tunnel-junction elements","volume":"43","author":"lee","year":"2007","journal-title":"IEEE Trans Magn"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647611"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1366230.1366262"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1063\/1.3499427"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2009.03.129"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"554","DOI":"10.1145\/1391469.1391610","article-title":"circuit and microarchitecture evaluation of 3d stacking magnetic ram (mram) as a universal memory replacement","author":"xiangyu dong","year":"2008","journal-title":"2008 45th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1063\/1.2719032"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/20.908581"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2012.2185311"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1002\/9780470891179"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2011.2158344"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1088\/0953-8984\/23\/5\/053202"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1063\/1.3676052"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.810048"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"205","DOI":"10.1126\/science.1120506","article-title":"Majority logic gate for magnetic quantum-dot cellular automata","volume":"311","author":"imre","year":"2006","journal-title":"Science"},{"key":"ref1","first-page":"862","volume":"3","author":"yuasa","year":"2004","journal-title":"Giant room-temperature magnetoresistance in single-crystal Fe\/MgO\/Fe magnetic tunnel junctions"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1143\/APEX.1.091301"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2011.2156379"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2010.31"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283787"},{"key":"ref23","author":"givone","year":"2003","journal-title":"Digital Principles and Design"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2010.5682957"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2010.5510929"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6690268\/06531668.pdf?arnumber=6531668","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,11,29]],"date-time":"2021-11-29T20:54:47Z","timestamp":1638219287000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6531668\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,1]]},"references-count":29,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2012.2236690","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,1]]}}}