{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T17:34:05Z","timestamp":1783618445535,"version":"3.55.0"},"reference-count":17,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2014,2,1]],"date-time":"2014-02-01T00:00:00Z","timestamp":1391212800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/tvlsi.2013.2239321","type":"journal-article","created":{"date-parts":[[2013,2,4]],"date-time":"2013-02-04T19:02:40Z","timestamp":1360004560000},"page":"362-371","source":"Crossref","is-referenced-by-count":54,"title":["Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay"],"prefix":"10.1109","volume":"22","author":[{"given":"Pramod Kumar","family":"Meher","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sang Yoon","family":"Park","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"359","DOI":"10.1109\/82.933794","article-title":"An efficient systolic architecture for the DLMS adaptive filter and its applications","volume":"48","author":"van","year":"2001","journal-title":"IEEE Trans Circuits Syst II Analog Digital Signal Process"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.840403"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937516"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2011.6026642"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2011.6026643"},{"key":"ref15","author":"parhi","year":"1999","journal-title":"VLSI Digital Signal Procesing Systems Design and Implementation"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1984.1164286"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2004.1327091"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/29.31293"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1990.112086"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/78.165667"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/78.157202"},{"key":"ref8","first-page":"286","article-title":"A systolic architecture for LMS adaptive filtering with minimal adaptation delay","author":"ramanathan","year":"1996","journal-title":"Proc Int Conf Very Large Scale Integration (VLSI) Systems Design"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/82.251841"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1002\/0471461288"},{"key":"ref1","author":"widrow","year":"1985","journal-title":"Adaptive Signal Processing"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1023\/B:VLSI.0000047275.54691.be"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/92\/6716075\/06449328.pdf?arnumber=6449328","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:31:42Z","timestamp":1642005102000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6449328\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":17,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2239321","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,2]]}}}