{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,2]],"date-time":"2026-09-02T17:53:56Z","timestamp":1788371636523,"version":"build-2803163510"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1109\/tvlsi.2013.2248764","type":"journal-article","created":{"date-parts":[[2013,4,15]],"date-time":"2013-04-15T14:41:39Z","timestamp":1366036899000},"page":"516-521","source":"Crossref","is-referenced-by-count":13,"title":["Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing"],"prefix":"10.1109","volume":"22","author":[{"given":"Samah Mohamed","family":"Saeed","sequence":"first","affiliation":[{"name":"Computer Science Department, New York University Polytechnic Institute, New York, NY, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ozgur","family":"Sinanoglu","sequence":"additional","affiliation":[{"name":"Department of Computer Engineering, New York University Abu Dhabi, Abu Dhabi, UAE"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355649"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2006.18"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469590"},{"key":"ref13","first-page":"1","article-title":"Pattern-directed circuit virtual partitioning for test power reduction","author":"xu","year":"2007","journal-title":"Proc Int Test Conf"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469580"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2011.5941434"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1999.810734"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2006.4380823"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006091"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654124"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/43.238615"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.35"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/92.311647"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-0928-2"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1003802"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1386971"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271098"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2012.6233001"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2008.86"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2011.18"},{"key":"ref20","first-page":"534","article-title":"Interactive presentation: On power-profiling and pattern generation for power-safe scan tests","author":"devanathan","year":"2007","journal-title":"Proc Design Autom Test Eur Conf"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2008.13"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484837"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.829797"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419834"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923456"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/92.748202"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6746074\/06502264.pdf?arnumber=6502264","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,22]],"date-time":"2025-07-22T18:09:25Z","timestamp":1753207765000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6502264\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3]]},"references-count":27,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2248764","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,3]]}}}