{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,25]],"date-time":"2026-09-25T22:03:00Z","timestamp":1790373780591,"version":"4.1.0"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1109\/tvlsi.2013.2251919","type":"journal-article","created":{"date-parts":[[2013,3,28]],"date-time":"2013-03-28T18:02:14Z","timestamp":1364493734000},"page":"497-506","source":"Crossref","is-referenced-by-count":19,"title":["Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches"],"prefix":"10.1109","volume":"22","author":[{"given":"Hari","family":"Chauhan","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yongsuk","family":"Choi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Marvin","family":"Onabajo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"In-Seok","family":"Jung","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yong-Bin","family":"Kim","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref38","year":"2011","journal-title":"Open-Access 45 nm PDK"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TASSP.1985.1164729"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2006.381812"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.841599"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/4.748183"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2126390"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2022993"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.845972"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/EIT.2011.5978612"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2005.63"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.881561"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2008.24"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2009454"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2020940"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-009-5136-0"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"2221","DOI":"10.1109\/JSSC.2003.819086","article-title":"A single-chip digitally calibrated 5.15-5.825-GHz 0.18-<formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\mu{\\rm m}$<\/tex><\/formula> CMOS transceiver for 802.11a wireless LAN","volume":"38","author":"vassiliou","year":"2003","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1049\/el.2010.2644"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/82.754864"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.852007"},{"key":"ref28","year":"2002","journal-title":"Selecting the Optimum Test Tones and Test Equipment for Successful High-Speed ADC Sinewave Testing"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/LMWC.2003.819379"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/54.485784"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2006.870317"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1049\/el:20082895"},{"key":"ref29","first-page":"189","article-title":"Selecting test frequencies for sinewave tests of ADCs","author":"blair","year":"2002","journal-title":"Proc IEEE Instrum Meas Technol Conf"},{"key":"ref5","first-page":"178","article-title":"A self-tuning technique for optimization of dual band LNA","author":"ahsan","year":"2008","journal-title":"Proc European Conf Wireless Technology"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537437"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LMWC.2008.2002463"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"718","DOI":"10.1109\/JSSC.2009.2013762","article-title":"A single?chip 10-band WCDMA\/HSDPA 4-band GSM\/EDGE SAW-less CMOS receiver with DigRF 3G interface and <formula formulatype=\"inline\"> <tex Notation=\"TeX\">${+}{\\rm 90}~{\\rm dBm}$<\/tex><\/formula> IIP2","volume":"44","author":"kaczman","year":"2009","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2037476"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.33"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.910771"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/19.982947"},{"key":"ref21","first-page":"4523","article-title":"A low-power 64-point FFT\/IFFT design for IEEE 802.11a WLAN application","author":"lin","year":"2006","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref24","year":"2008","journal-title":"IEEE Standard for Digitizing Waveform Recorders"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"361","DOI":"10.1016\/j.measurement.2006.06.016","article-title":"Choice of the cosine-class windows for ADC dynamic testing by spectral analysis","volume":"40","author":"belega","year":"2007","journal-title":"Measurement"},{"key":"ref26","author":"burns","year":"2000","journal-title":"An Introduction to Mixed-Signal IC Test and Measurement"},{"key":"ref25","year":"2011","journal-title":"IEEE Standard for Terminology and Test Methods for Analog to Digital Converters"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6746074\/06490077.pdf?arnumber=6490077","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:31:43Z","timestamp":1642005103000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6490077\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3]]},"references-count":38,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2251919","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,3]]}}}