{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:11:40Z","timestamp":1758892300312,"version":"3.41.2"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1109\/tvlsi.2013.2252030","type":"journal-article","created":{"date-parts":[[2013,4,23]],"date-time":"2013-04-23T14:48:00Z","timestamp":1366728480000},"page":"641-654","source":"Crossref","is-referenced-by-count":10,"title":["Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains"],"prefix":"10.1109","volume":"22","author":[{"given":"Jean-Michel","family":"Chabloz","sequence":"first","affiliation":[{"name":"Department of Electronic Systems, School of ICT, KTH—Royal Institute of Technology, Stockholm, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ahmed","family":"Hemani","sequence":"additional","affiliation":[{"name":"Department of Electronic Systems, School of ICT, KTH—Royal Institute of Technology, Stockholm, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","first-page":"271","article-title":"Rational clocking","author":"sarmenta","year":"1995","journal-title":"Proc Int Conf Comput Design"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2009.5071473"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2003.1199169"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/NORCHP.2006.329234"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2006.18"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2000.836791"},{"key":"ref37","first-page":"1414","article-title":"Developing mesochronous synchronizers to enable 3-D NoCs","author":"loi","year":"2008","journal-title":"Proc Design Autom Test Eur Conf Exhibit"},{"key":"ref36","first-page":"1","article-title":"Asynchronous FIFO interfaces for GALS on-chip switched networks","author":"kim","year":"2005","journal-title":"Proc Int SoC Design Conf"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2004.1299298"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/4.982426"},{"key":"ref10","first-page":"139","article-title":"Physical implementation of the DSPIN network-on-chip in the FAUST architecture","author":"panades","year":"2008","journal-title":"Proc IEEE 1st Int Symp Netw -on-Chip"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2006.19"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.15"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2010.14"},{"journal-title":"Computers Without Clocks","year":"2002","author":"sutherland","key":"ref13"},{"key":"ref14","article-title":"Does Asynchronous logic design really have a future?","author":"borkar","year":"2003","journal-title":"EE Times"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364396"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1016720.1016764"},{"key":"ref17","first-page":"38","article-title":"Implementing a STARI chip","author":"greenstreet","year":"1995","journal-title":"Proc Int Conf Comput Design VLSI Comput Process"},{"journal-title":"Globally asynchronous locally synchronous systems","year":"1984","author":"chapiro","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.782202"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"78","DOI":"10.1109\/ASYNC.2003.1199168","article-title":"Efficient self-timed interfaces for crossing clock domains","author":"chakraborty","year":"2003","journal-title":"Proc Int Symp Asynchron Syst Circuits"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910957"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/NANONET.2006.346236"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.151"},{"journal-title":"Digital Integrated Circuits A Design Perspective","year":"1995","author":"rabaey","key":"ref6"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2010.20"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.164"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283790"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"2009","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269205"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2009.197"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1990.186126"},{"key":"ref20","first-page":"109","article-title":"A flexible interface for rationally-related frequencies","author":"chabloz","year":"2009","journal-title":"Proc Int l Conf Circuit Design"},{"key":"ref22","first-page":"247","article-title":"Distributed DVFS with rationally-related frequencies and quantized voltage levels","author":"chabloz","year":"2010","journal-title":"Proc Int Symp Low-Power Electron Design"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647563"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2006.48"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1996.563543"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/82.917781"},{"key":"ref25","first-page":"1","article-title":"Simulation and synthesis techniques for asynchronous FIFO design with asynchronous pointer comparisons","author":"cummings","year":"2002","journal-title":"Proc Symp Users Group Conf"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6746074\/06507330.pdf?arnumber=6507330","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,22]],"date-time":"2025-07-22T18:09:24Z","timestamp":1753207764000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6507330\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3]]},"references-count":40,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2252030","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2014,3]]}}}