{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,24]],"date-time":"2025-11-24T23:40:59Z","timestamp":1764027659858,"version":"3.41.2"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2014,3,1]],"date-time":"2014-03-01T00:00:00Z","timestamp":1393632000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1109\/tvlsi.2013.2252031","type":"journal-article","created":{"date-parts":[[2013,4,15]],"date-time":"2013-04-15T14:41:39Z","timestamp":1366036899000},"page":"548-561","source":"Crossref","is-referenced-by-count":29,"title":["Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs"],"prefix":"10.1109","volume":"22","author":[{"given":"Ajay N.","family":"Bhoj","sequence":"first","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Niraj K.","family":"Jha","sequence":"additional","affiliation":[{"name":"Princeton University, Princeton, NJ, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077607"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2019279"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2007.182"},{"journal-title":"Sentaurus TCAD Tool Suite","year":"2008","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2011.6081799"},{"key":"ref15","first-page":"16","article-title":"Modeling of width-quantization-induced variations in logic FinFETs for 22 nm and beyond","author":"lin","year":"2011","journal-title":"Proc Int Symp VLSI Technol"},{"journal-title":"Fabless-foundry model under stress","year":"2012","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770805"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VTSA.2005.1497065"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-6606-3"},{"key":"ref4","first-page":"64","article-title":"A 0.021 <formula formulatype=\"inline\"><tex Notation=\"TeX\">$\\mu{\\rm m}^{2}$<\/tex><\/formula> trigate SRAM cell with aggressively scaled gate and contact pitch","author":"guillorn","year":"2011","journal-title":"Proc Int Symp VLSI Technol"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424366"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2010818"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2001941"},{"key":"ref8","first-page":"63","article-title":"Independent-gate four-terminal FinFET SRAM for drastic leakage current reduction","author":"endo","year":"2008","journal-title":"Proc Int Integrated Circuit Design and Technology Conf"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796792"},{"key":"ref2","first-page":"19","article-title":"A 0.063 <formula formulatype=\"inline\"> <tex Notation=\"TeX\">$\\mu{\\rm m}^{2}$<\/tex><\/formula> FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch","author":"basker","year":"2010","journal-title":"Proc Int Symp VLSI Technology"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2008.4815583"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.2004.1263404"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.883344"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2012.2210421"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2011.2175359"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2011.6131673"},{"key":"ref23","article-title":"3-D-TCAD based parasitic capacitance extraction for emerging multi-gate devices and circuits","author":"bhoj","year":"0","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.Design.2010.88"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6746074\/06502262.pdf?arnumber=6502262","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,22]],"date-time":"2025-07-22T18:09:25Z","timestamp":1753207765000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6502262\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,3]]},"references-count":25,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2252031","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2014,3]]}}}