{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:07:56Z","timestamp":1759147676652},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2014,4,1]],"date-time":"2014-04-01T00:00:00Z","timestamp":1396310400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,4]]},"DOI":"10.1109\/tvlsi.2013.2252032","type":"journal-article","created":{"date-parts":[[2013,4,18]],"date-time":"2013-04-18T18:07:26Z","timestamp":1366308446000},"page":"759-770","source":"Crossref","is-referenced-by-count":16,"title":["32 Bit $\\times\\,$32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler"],"prefix":"10.1109","volume":"22","author":[{"given":"Xiaoxiao","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Farid","family":"Boussaid","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amine","family":"Bermak","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000730"},{"key":"ref10","first-page":"-553i","article-title":"Variable-precision multiplier for equalizer with adaptive modulation","volume":"1","author":"ling","year":"2004","journal-title":"Proc 43rd MidWest Symp Circuits Syst"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.840765"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1464922"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20060156"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.1991.155233"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:19971478"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICVC.1999.820930"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/4.881202"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/4.661211"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.838021"},{"key":"ref28","first-page":"300","article-title":"Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90 nm CMOS","author":"calhoun","year":"2005","journal-title":"IEEE Int Solid-State Circuits Conf Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICVC.1999.820930"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007145"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2003.1231919"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2009.2023763"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:20020423"},{"key":"ref5","first-page":"123","article-title":"A power-aware scalable pipelined booth multiplier","author":"lee","year":"2004","journal-title":"Proc IEEE Int SOC Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000457"},{"key":"ref7","first-page":"938","article-title":"A multiplexer-based concept for reconfigurable multiplier arrays","volume":"3203","author":"pfander","year":"2004","journal-title":"Proc Int Conf Field Program Logic Appl"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/92.974890"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1329264"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MWC.2002.1028875"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.156"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.833400"},{"key":"ref21","first-page":"656","article-title":"A Study on multiplier architecture optimized for 32-bit processor with 3-stage pipeline","author":"jeong","year":"2004","journal-title":"Proc Int SoC Design Conf"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629917"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.1999.777272"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870912"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2003.1253179"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6774899\/06504788.pdf?arnumber=6504788","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:31:44Z","timestamp":1642005104000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6504788\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4]]},"references-count":30,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2252032","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,4]]}}}