{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,10]],"date-time":"2025-12-10T08:35:17Z","timestamp":1765355717689,"version":"3.41.2"},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2014,4,1]],"date-time":"2014-04-01T00:00:00Z","timestamp":1396310400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2014,4,1]],"date-time":"2014-04-01T00:00:00Z","timestamp":1396310400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2014,4,1]],"date-time":"2014-04-01T00:00:00Z","timestamp":1396310400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,4]]},"DOI":"10.1109\/tvlsi.2013.2253338","type":"journal-article","created":{"date-parts":[[2013,5,6]],"date-time":"2013-05-06T14:02:10Z","timestamp":1367848930000},"page":"771-778","source":"Crossref","is-referenced-by-count":43,"title":["Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating"],"prefix":"10.1109","volume":"22","author":[{"given":"Shmuel","family":"Wimer","sequence":"first","affiliation":[{"name":"Electrical Engineering Faculty, Technion–Israel Institute of Technology, Haifa, Israel"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Israel","family":"Koren","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/ICCAD.2010.5654155"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1145\/1960397.1960424"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1145\/966747.966750"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1016\/j.vlsi.2004.08.001"},{"year":"2009","journal-title":"Low Skew?Low Power CTS Methodology in SOC Encounter for ARM Processor Cores","key":"ref14"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/TCSII.2007.914901"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1007\/s12532-009-0002-8"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1137\/1018115"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/LPE.2002.146755"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/ISVLSI.2007.20"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/LPE.2002.146755"},{"key":"ref3","first-page":"143","article-title":"Low power clocking strategies in deep submicron technologies","author":"hosny","year":"2008","journal-title":"IEEE Int Conf Integrated Circuit Design and Technology"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1145\/1353629.1353668"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/43.924824"},{"year":"0","journal-title":"SpyGlass Power","key":"ref8"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1145\/981066.981097"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/92.845896"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/TVLSI.2011.2162861"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1002\/0471723703"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1016\/j.cor.2006.04.002"},{"year":"0","journal-title":"CEVA-XC4000","key":"ref22"},{"year":"0","journal-title":"CEVA-X1643","key":"ref21"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1007\/978-3-642-11802-9_14"},{"year":"0","key":"ref23"},{"year":"2010","journal-title":"Synopsys Design Compiler","key":"ref26"},{"year":"2012","journal-title":"AGE A 3D graphics acceleration engine","key":"ref25"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6774899\/06514050.pdf?arnumber=6514050","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,22]],"date-time":"2025-07-22T18:09:30Z","timestamp":1753207770000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6514050\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4]]},"references-count":26,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2253338","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2014,4]]}}}