{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,4]],"date-time":"2026-10-04T22:30:56Z","timestamp":1791153056937,"version":"4.1.0"},"reference-count":16,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2014,4,1]],"date-time":"2014-04-01T00:00:00Z","timestamp":1396310400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2014,4,1]],"date-time":"2014-04-01T00:00:00Z","timestamp":1396310400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2014,4,1]],"date-time":"2014-04-01T00:00:00Z","timestamp":1396310400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,4]]},"DOI":"10.1109\/tvlsi.2013.2256945","type":"journal-article","created":{"date-parts":[[2013,5,7]],"date-time":"2013-05-07T15:52:14Z","timestamp":1367941934000},"page":"712-720","source":"Crossref","is-referenced-by-count":33,"title":["AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture"],"prefix":"10.1109","volume":"22","author":[{"given":"Kon-Woo","family":"Kwon","sequence":"first","affiliation":[{"name":"Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sri Harsha","family":"Choday","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yusung","family":"Kim","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kaushik","family":"Roy","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering Department, Purdue University, West Lafayette, IN, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176592"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2011.2169456"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176595"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.831471"},{"key":"ref14","year":"2011","journal-title":"SimpleScalar"},{"key":"ref15","year":"2000","journal-title":"SPEC2000"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2009.5424242"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1840845.1840931"},{"key":"ref3","first-page":"554","article-title":"Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement","author":"dong","year":"2008","journal-title":"Proc 40th Design Autom Conf"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228447"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749716"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687448"},{"key":"ref7","first-page":"239","article-title":"A novel architecture of the 3D stacked MRAM L2 cache for CMPs","author":"sun","year":"2009","journal-title":"Proc IEEE Int Symp High Perform Comput Arch"},{"key":"ref2","first-page":"1","article-title":"45 nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T\/1MTJ cell","author":"lin","year":"2009","journal-title":"Proc IEEE Int Electron Devices Meeting"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555761"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609379"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6774899\/06514685.pdf?arnumber=6514685","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,22]],"date-time":"2025-07-22T18:09:31Z","timestamp":1753207771000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6514685\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4]]},"references-count":16,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2256945","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,4]]}}}