{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T09:16:03Z","timestamp":1763457363145,"version":"3.37.3"},"reference-count":24,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2014,5,1]],"date-time":"2014-05-01T00:00:00Z","timestamp":1398902400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council","doi-asserted-by":"publisher","award":["NSC-101-2221-E-194-063"],"award-info":[{"award-number":["NSC-101-2221-E-194-063"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,5]]},"DOI":"10.1109\/tvlsi.2013.2260186","type":"journal-article","created":{"date-parts":[[2013,6,4]],"date-time":"2013-06-04T18:01:51Z","timestamp":1370368911000},"page":"1096-1105","source":"Crossref","is-referenced-by-count":20,"title":["High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology"],"prefix":"10.1109","volume":"22","author":[{"given":"Ching-Che","family":"Chung","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Duo","family":"Sheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sung-En","family":"Shen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"925","article-title":"An all-digital 50% duty-cycle corrector","author":"wang","year":"0","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT.2006.258158"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.885396"},{"key":"ref13","first-page":"373","article-title":"An all-digital 90-degree phase-shift DLL with loop-embedded DCC for 1.6 Gbps DDR Interface","author":"bae","year":"0","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2047994"},{"key":"ref15","first-page":"325","article-title":"A 500 MHz DLL with second order duty cycle corrector for low jitter","author":"kim","year":"0","journal-title":"Proc IEEE Custom Integr Circuits Conf"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2021447"},{"key":"ref17","first-page":"1","article-title":"A high-resolution all-digital duty-cycle corrector with a new pulse-width detector","author":"ke","year":"0","journal-title":"Proc IEEE Conf Electron Devices Solid-State Circuits"},{"key":"ref18","first-page":"82","article-title":"A 0.17–1.4 GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme","author":"shin","year":"0","journal-title":"Proc Eur Solid-State Circuits Conf"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.922712"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914286"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.822781"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.874326"},{"key":"ref5","first-page":"1258","article-title":"An all-digital pulsewidth control loop","author":"wang","year":"0","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"760","DOI":"10.1109\/TVLSI.2011.2111424","article-title":"All-digital wide range precharge logic 50% duty cycle corrector","volume":"20","author":"gu","year":"2012","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.845988"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.803050"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.823439"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/EDSSC.2007.4450134"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2047435"},{"key":"ref22","first-page":"267","article-title":"A high-resolution all-digital phase-lock loop with its application to built-in speed grading for memory","author":"hsu","year":"0","journal-title":"Proc IEEE Symp VLSI Design Autom"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2040306"},{"key":"ref24","first-page":"257","article-title":"A programmable, multi-GHz, wide-range duty cycle correction circuit in 45 nm CMOS process","author":"mehta","year":"0","journal-title":"Proc Eur Solid-Stage Circuits Conf"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.903782"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6803904\/06523125.pdf?arnumber=6523125","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:17:08Z","timestamp":1642004228000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6523125\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5]]},"references-count":24,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2260186","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2014,5]]}}}