{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:12Z","timestamp":1740133272077,"version":"3.37.3"},"reference-count":22,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2014,6,1]],"date-time":"2014-06-01T00:00:00Z","timestamp":1401580800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council","doi-asserted-by":"publisher","award":["NSC101-2221-E009-166"],"award-info":[{"award-number":["NSC101-2221-E009-166"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Ministry of Economic Affairs, Taiwan","award":["94-EC-17-A-01-S1-002","95-EC-17-A-01-S1-037","96-EC-17-A-01-S1-037"],"award-info":[{"award-number":["94-EC-17-A-01-S1-002","95-EC-17-A-01-S1-037","96-EC-17-A-01-S1-037"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/tvlsi.2013.2270362","type":"journal-article","created":{"date-parts":[[2013,10,7]],"date-time":"2013-10-07T18:08:17Z","timestamp":1381169297000},"page":"1238-1247","source":"Crossref","is-referenced-by-count":3,"title":["14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability"],"prefix":"10.1109","volume":"22","author":[{"given":"Hao-Chiao","family":"Hong","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yung-Shun","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei-Chieh","family":"Fang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/JSSC.2003.818567"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/TCSI.2005.862068"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/JSSC.1987.1052715"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"102","DOI":"10.1109\/LPE.2000.155261","article-title":"mos current mode logic for low power, low noise cordic computation in mixed-signal environments","author":"musicer","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/92.711317"},{"key":"ref15","first-page":"1193","article-title":"SFDR-bandwidth limitations for high speed high resolution current steering CMOS D\/A converters","volume":"3","author":"den bosch","year":"1999","journal-title":"Proc IEEE"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/TVLSI.2009.2013628"},{"key":"ref17","first-page":"544","article-title":"A 24 GS\/s 6b ADC in 90 nm CMOS","author":"schvan","year":"2008","journal-title":"IEEE ISSCC Dig Tech Papers"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/JSSC.2009.2020657"},{"year":"2002","author":"allen","journal-title":"CMOS Analog Circuit Design","key":"ref19"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/TVLSI.2011.2157842"},{"key":"ref3","article-title":"Serdes about to get extreme makeover: ISSCC panel debates move toward ADCs","author":"merritt","year":"2009","journal-title":"Electron Eng Times"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/4.962288"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/TVLSI.2010.2096438"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/JSSC.2002.808282"},{"key":"ref7","first-page":"1162","article-title":"A 10-Gb\/s, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs","volume":"2","author":"park","year":"0","journal-title":"Proc IEEE ISCAS"},{"year":"2010","journal-title":"IEEE P802 3ba 40 Gb\/s and 100 Gb\/s Ethernet Task Force","key":"ref2"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/ICCAD.2005.1560126"},{"key":"ref9","first-page":"416","article-title":"10 GSamples\/s, 4-bit, 1.2 V, design-for-testability ADC and DAC in 0.13 $\\mu{\\rm m}$ CMOS technology","author":"liang","year":"0","journal-title":"Proc IEEE ASSCC"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/JSSC.2007.903053"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/CICC.2011.6188616"},{"key":"ref21","first-page":"1","article-title":"A 4-bit 12 GS\/s data acquisition system-on-chip including a flash ADC and 4-channel DeMUX in 130 nm CMOS","author":"javid","year":"0","journal-title":"Proc IEEE CICC"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6819107\/06623173.pdf?arnumber=6623173","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:18:00Z","timestamp":1642004280000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6623173\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":22,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2270362","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2014,6]]}}}