{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T05:45:10Z","timestamp":1761975910878,"version":"build-2065373602"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2014,6,1]],"date-time":"2014-06-01T00:00:00Z","timestamp":1401580800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-0964514","ECCS-1002237"],"award-info":[{"award-number":["CCF-0964514","ECCS-1002237"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/tvlsi.2013.2271696","type":"journal-article","created":{"date-parts":[[2013,8,1]],"date-time":"2013-08-01T18:02:51Z","timestamp":1375380171000},"page":"1314-1327","source":"Crossref","is-referenced-by-count":14,"title":["Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks"],"prefix":"10.1109","volume":"22","author":[{"given":"Anandaroop","family":"Ghosh","sequence":"first","affiliation":[]},{"given":"Somnath","family":"Paul","sequence":"additional","affiliation":[]},{"given":"Jongsun","family":"Park","sequence":"additional","affiliation":[]},{"given":"Swarup","family":"Bhunia","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2011.58"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993675"},{"journal-title":"Time Dependent Schrodinger Equation","year":"2009","key":"ref31"},{"journal-title":"Numerical Recipes in FORTRAN","year":"1992","author":"press","key":"ref30"},{"journal-title":"The role of distributed arithmetic in FPGA-based signal processing","year":"2005","key":"ref36"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283813"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2088142"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2010.07.013"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311200"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/AHS.2008.71"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2008.39"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2005.1568543"},{"journal-title":"Power consumption at 40 and 45 nm","year":"2009","author":"klein","key":"ref15"},{"journal-title":"FPGA Logic Cells Comparison","year":"2009","key":"ref16"},{"journal-title":"FPGA architectures","year":"2006","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/611817.611850"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.54"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/1015330.1015408"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/611843.611844"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/82.592582"},{"journal-title":"Achieving Low Power in 65-nm Cyclone III FPGAs","year":"2007","key":"ref3"},{"journal-title":"Xilinx Virtex Series of FPGAs","year":"2013","key":"ref6"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2010.2076281"},{"journal-title":"Stratix FPGA Low Power High Performance","year":"2013","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275138"},{"key":"ref7","article-title":"AES on FPGA from the fastest to the smallest","author":"good","year":"2005","journal-title":"Cryptographic Hardware and Embedded Systems"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.810003"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275137"},{"journal-title":"Embedded Intel Solutions","year":"2010","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/12.372037"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/AERO.1999.793177"},{"journal-title":"The Landscape of Parallel Computing Research A View from Berkeley","year":"2006","key":"ref21"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887924"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.2009.5336225"},{"journal-title":"XPower Estimator User Guide","year":"2012","key":"ref26"},{"journal-title":"PowerPlay Power Estimator","year":"2012","key":"ref25"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6819107\/06573396.pdf?arnumber=6573396","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:18:00Z","timestamp":1642004280000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6573396\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":36,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2271696","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2014,6]]}}}