{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:58:01Z","timestamp":1759147081181},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2014,7,1]],"date-time":"2014-07-01T00:00:00Z","timestamp":1404172800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"CATRENE programme's Computing Fabric for High Performance Computing"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,7]]},"DOI":"10.1109\/tvlsi.2013.2273003","type":"journal-article","created":{"date-parts":[[2013,7,24]],"date-time":"2013-07-24T22:52:21Z","timestamp":1374706341000},"page":"1606-1619","source":"Crossref","is-referenced-by-count":6,"title":["System Level Methodology for Interconnect Aware and Temperature Constrained Power Management of 3-D MP-SOCs"],"prefix":"10.1109","volume":"22","author":[{"given":"Sumeet S.","family":"Kumar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arnica","family":"Aggarwal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Radhika Sanjeev","family":"Jagtap","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amir","family":"Zjajo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rene","family":"van Leuken","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/WWC.2001.990739"},{"key":"ref38","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2008.4658631"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/1346281.1346289"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187483"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681639"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893649"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2011.5941443"},{"key":"ref34","author":"aggarwal","year":"2011","journal-title":"Temperature-constrained power management scheme for 3D MPSoC"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2006.1594714"},{"key":"ref40","author":"jagtap","year":"2011","journal-title":"A Methodology for Early Exploration of TSV Interconnects in 3D Stacked ICs"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2012.9"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SaPIW.2012.6222899"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2010.5751452"},{"key":"ref14","first-page":"130","article-title":"Design and management of 3D chip multiprocessors using network-in-memory","author":"li","year":"0","journal-title":"Proc Int Symp Comput Archit"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024900"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2009.5306541"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419899"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703278"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2026200"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804385"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653749"},{"key":"ref27","first-page":"31.2.1","article-title":"Thermal analysis of heterogeneous 3D ICs with various integration scenarios","author":"chiang","year":"0","journal-title":"IEDM Tech Dig"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289846"},{"key":"ref29","first-page":"409","article-title":"Fast thermal analysis for VLSI circuits via semi-analytical Green's function in multi-layer materials","volume":"2","author":"wang","year":"0","journal-title":"Proc Int Symp Circuits Syst"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ITHERM.2008.4544389"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2006.1594713"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168873"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.77"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"181","DOI":"10.1109\/TCPMT.2010.2101890","article-title":"High-frequency scalable electrical model and analysis of a through silicon via (TSV)","volume":"1","author":"kim","year":"2011","journal-title":"IEEE Trans Compon Packag Manuf Technol"},{"key":"ref20","year":"2010","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2011.39"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283790"},{"key":"ref42","first-page":"123","article-title":"System level analysis of fast, per-core DVFS using on-chip switching regulators","author":"kim","year":"0","journal-title":"Proc Int Symp High Perform Comput Archit"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5938046"},{"key":"ref41","year":"2008","journal-title":"Predictive Technology Model"},{"key":"ref23","doi-asserted-by":"crossref","first-page":"1479","DOI":"10.1109\/TCAD.2008.925793","article-title":"Three-dimensional chip-multiprocessor run-time thermal management","volume":"27","author":"zhu","year":"2008","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/SMICND.1999.810382"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6841655\/06567999.pdf?arnumber=6567999","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:17:30Z","timestamp":1642004250000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6567999\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7]]},"references-count":42,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2273003","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,7]]}}}