{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T14:52:41Z","timestamp":1761663161111,"version":"3.37.3"},"reference-count":17,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2014,7,1]],"date-time":"2014-07-01T00:00:00Z","timestamp":1404172800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/100004361","name":"Texas Instruments","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004361","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,7]]},"DOI":"10.1109\/tvlsi.2013.2275571","type":"journal-article","created":{"date-parts":[[2013,8,28]],"date-time":"2013-08-28T20:18:37Z","timestamp":1377721117000},"page":"1515-1525","source":"Crossref","is-referenced-by-count":18,"title":["Memory-Hierarchical and Mode-Adaptive HEVC Intra Prediction Architecture for Quad Full HD Video Decoding"],"prefix":"10.1109","volume":"22","author":[{"given":"Chao-Tsung","family":"Huang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mehul","family":"Tikekar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anantha P.","family":"Chandrakasan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"2931","article-title":"Architecture design of H.264\/AVC decoder with hybrid task pipelining for high definition videos","volume":"3","author":"chen","year":"0","journal-title":"Proc IEEE Int Symp Circuits Syst"},{"key":"ref11","first-page":"932","article-title":"Low complexity architecture design of H.264 predictive pixel compensator for HDTV application","volume":"3","author":"chen","year":"0","journal-title":"Proc IEEE Int Conf Acoust Speech Signal Process"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"302","DOI":"10.1109\/TVLSI.2007.915377","article-title":"A power-efficient and self-adaptive prediction engine for H.264\/AVC decoding","volume":"16","author":"xu","year":"2008","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref13","first-page":"57","article-title":"High profile intra prediction architecture for H.264","author":"he","year":"0","journal-title":"Proc IEEE ISOCC"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2011.2171213"},{"key":"ref15","first-page":"373","article-title":"An efficient VLSI architecture for 4 $\\,\\times\\,$ 4 intra prediction in the high efficiency video coding (HEVC) standard","author":"li","year":"0","journal-title":"Proc 18th IEEE Int Conf Image Process"},{"key":"ref16","first-page":"719","article-title":"A high performance and low energy intra prediction hardware for HEVC video decoding","author":"kalali","year":"0","journal-title":"Proc DASIP"},{"journal-title":"High Efficiency Video Coding Test Model (HM) 7 0","year":"2012","key":"ref17"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2012.2221192"},{"journal-title":"Advanced Video Coding","year":"2010","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2010.2092613"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2012.2221525"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2012.6272182"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MMSP.2011.6093806"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2012.2221191"},{"journal-title":"High Efficiency Video Coding (HEVC) Text Specification Draft 10 (for FDIS and Last Call)","year":"2013","author":"bross","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2012.2223013"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6841655\/06587591.pdf?arnumber=6587591","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:17:30Z","timestamp":1642004250000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6587591\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7]]},"references-count":17,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2275571","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2014,7]]}}}