{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,10]],"date-time":"2026-09-10T23:04:39Z","timestamp":1789081479325,"version":"build-2803163510"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2014,7,1]],"date-time":"2014-07-01T00:00:00Z","timestamp":1404172800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100001868","name":"National Science Council","doi-asserted-by":"publisher","award":["NSC-100-2221-E-194-051"],"award-info":[{"award-number":["NSC-100-2221-E-194-051"]}],"id":[{"id":"10.13039\/501100001868","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,7]]},"DOI":"10.1109\/tvlsi.2013.2275737","type":"journal-article","created":{"date-parts":[[2014,6,23]],"date-time":"2014-06-23T15:42:27Z","timestamp":1403538147000},"page":"1470-1480","source":"Crossref","is-referenced-by-count":30,"title":["Partial Parity Cache and Data Cache Management Method to Improve the Performance of an SSD-Based RAID"],"prefix":"10.1109","volume":"22","author":[{"given":"Ching-Che","family":"Chung","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hao-Hsiang","family":"Hsu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"crossref","first-page":"80","DOI":"10.1109\/TC.2010.197","article-title":"Flash-aware RAID Techniques for dependable and high-performance flash memory SSD","volume":"60","author":"im","year":"2011","journal-title":"IEEE Trans Comput"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICDCS.2009.27"},{"key":"ref12","first-page":"57","article-title":"Design tradeoffs for SSD performance","author":"agrawal","year":"0","journal-title":"Proc USENIX ATC"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2093139.2093143"},{"key":"ref14","first-page":"278","article-title":"I-CASH: Intelligently coupled array of SSD and HDD","author":"gen","year":"0","journal-title":"Proc HPCA"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/NAS.2010.9"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCIT.2009.5341269"},{"key":"ref17","article-title":"Building flexible, fault-tolerant flash-based storage systems","author":"greenan","year":"0","journal-title":"Proc HotDep"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1629435.1629459"},{"key":"ref19","year":"0","journal-title":"Iozone file system benchmark"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1587\/elex.9.1874"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2010.14"},{"key":"ref6","year":"2010","journal-title":"Solid State Drives for Enterprise Data Center Environments"},{"key":"ref5","first-page":"104","article-title":"Datacenter power savings through high ambient datacenter operation: CFD modeling study","author":"nishi","year":"0","journal-title":"Proc IEEE SEMI-THERM"},{"key":"ref8","author":"schulz","year":"2007","journal-title":"Achieving Energy Efficiency Using Flash SSD"},{"key":"ref7","author":"reinsel","year":"2008","journal-title":"Datacenter SSDs Solid Footing for Growth"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.14"},{"key":"ref1","first-page":"279","article-title":"The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization","author":"ho","year":"0","journal-title":"Proc ACM\/IEEE ISCA"},{"key":"ref9","year":"2007","journal-title":"HY27UK08BGFM NAND Flash Memories"},{"key":"ref20","year":"0","journal-title":"Postmark File System Benchmark Network Appliance"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6841655\/06579766.pdf?arnumber=6579766","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T11:17:31Z","timestamp":1641986251000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6579766\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7]]},"references-count":20,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2275737","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,7]]}}}