{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,12,20]],"date-time":"2023-12-20T00:33:16Z","timestamp":1703032396743},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2014,7,1]],"date-time":"2014-07-01T00:00:00Z","timestamp":1404172800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100004837","name":"Spanish Ministry of Science and Innovation","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100004837","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100008530","name":"European Regional Development Fund","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100008530","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,7]]},"DOI":"10.1109\/tvlsi.2013.2276738","type":"journal-article","created":{"date-parts":[[2013,10,21]],"date-time":"2013-10-21T20:08:08Z","timestamp":1382386088000},"page":"1557-1569","source":"Crossref","is-referenced-by-count":1,"title":["Sensitization Input Vector Impact on Propagation Delay for Nanometer CMOS ICs: Analysis and Solutions"],"prefix":"10.1109","volume":"22","author":[{"given":"Salvador","family":"Barcelo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xavier","family":"Gili","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sebastia","family":"Bota","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaume","family":"Segura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391589"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI.2008.92"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884860"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2008.41"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852674"},{"key":"ref15","first-page":"1","article-title":"Aging-aware timing analysis and optimization considering path sensitization","author":"wu","year":"0","journal-title":"Proc DATE"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469629"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629921"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/SOC.2003.1241550"},{"key":"ref19","article-title":"Scalable polynomial delay model for logic and physical synthesis","author":"wang","year":"0","journal-title":"Proceedings ICDAR"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1109\/MDT.2003.1232251","article-title":"Delay defect characteristics and testing strategies","volume":"20","author":"kim","year":"2003","journal-title":"IEEE Design Test Comput"},{"key":"ref27","year":"2010","journal-title":"PrimeTime Advanced Timing Analysis User Guide Version E-2010 12"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907047"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1998.727082"},{"key":"ref5","first-page":"325","article-title":"SPICE versus STA tools: Challenges and tips for better correlation","author":"motassadeq","year":"0","journal-title":"Proc IEEE SOCC"},{"key":"ref8","first-page":"450","article-title":"An efficient gate delay model for VLSI design","author":"ting-wei","year":"0","journal-title":"Proc 25th ICCD"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.2000.876003"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IWSTM.2000.869299"},{"key":"ref9","first-page":"17","article-title":"A normalized intrinsic delay model of static CMOS complex gates for deep submicron technologies","author":"xue","year":"0","journal-title":"Proc NEWCAS"},{"key":"ref1","first-page":"468","article-title":"Challenges in gate level modeling for delay and SI at 65 nm and below","author":"keller","year":"0","journal-title":"Proc 45th ACM\/IEEE DAC"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/43.331411"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/FTCSH.1995.532658"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825858"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763254"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/12.707585"},{"key":"ref26","doi-asserted-by":"crossref","first-page":"1089","DOI":"10.1109\/TCAD.2005.850891","article-title":"HyPE: Hybrid power estimation for IP-based systems-on-chip","volume":"24","author":"liu","year":"2005","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.895781"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6841655\/06642066.pdf?arnumber=6642066","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:17:30Z","timestamp":1642004250000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6642066\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,7]]},"references-count":27,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2276738","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,7]]}}}