{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,3]],"date-time":"2026-07-03T11:01:42Z","timestamp":1783076502107,"version":"3.54.6"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2014,8,1]],"date-time":"2014-08-01T00:00:00Z","timestamp":1406851200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,8]]},"DOI":"10.1109\/tvlsi.2013.2278025","type":"journal-article","created":{"date-parts":[[2013,9,11]],"date-time":"2013-09-11T19:26:09Z","timestamp":1378927569000},"page":"1803-1814","source":"Crossref","is-referenced-by-count":21,"title":["Orchestrating Cache Management and Memory Scheduling for GPGPU Applications"],"prefix":"10.1109","volume":"22","author":[{"given":"Shuai","family":"Mu","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yandong","family":"Deng","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yubei","family":"Chen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Huaiming","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jianming","family":"Pan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wenjun","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhihua","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/1806596.1806606"},{"key":"ref32","article-title":"Effect of instruction fetch and memory scheduling on GPU performance","author":"lakshminarayana","year":"2010","journal-title":"Workshop on Language Compiler and Architecture Support for GPGPU"},{"key":"ref31","first-page":"245","article-title":"Effective management of dram bandwidth in multi-core processors","author":"rafique","year":"2007","journal-title":"Proc Int Conf PACT"},{"key":"ref30","first-page":"63","article-title":"Parallelism-aware batch scheduling: Enhancing both performance and fairness of shared dram systems","author":"mutlu","year":"2008","journal-title":"Proc ISCA"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/1961296.1950408"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/1375527.1375562"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/1345206.1345220"},{"key":"ref10","author":"jacob","year":"2007","journal-title":"Memory Systems Cache DRAM Disk"},{"key":"ref11","first-page":"111","article-title":"Fair cache sharing and partitioning in a chip multiprocessor architecture","author":"kim","year":"2004","journal-title":"Proc Int Conf PACT"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815971"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555778"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815992"},{"key":"ref16","year":"2011","journal-title":"OpenCL Programming Guide"},{"key":"ref17","year":"2012","journal-title":"Getting Started With CUDA SDK SAMPLES"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2009.4919648"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2010.44"},{"key":"ref4","first-page":"93","article-title":"IP routing processing with graphics processors","author":"mu","year":"2010","journal-title":"Proc DATE"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1997.604734"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687501"},{"key":"ref6","author":"nickolls","year":"2011","journal-title":"Instructions for managing a parallel cache hierarchy"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.21"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICPADS.2011.29"},{"key":"ref8","year":"2012","journal-title":"CUDA Programming Guide 5 0"},{"key":"ref7","year":"2012","journal-title":"NVIDIA's Next Generation CUDA Computer Architecture Fermi"},{"key":"ref2","author":"kirk","year":"2010","journal-title":"Programming Massively Parallel Processors A Handson Approach"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCSim.2011.5999886"},{"key":"ref1","year":"2013","journal-title":"NVIDIA's Next Generation CUDA Computer Architecture Kepler GK110"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2012.6402918"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2001.970573"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6168947"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2011.32"},{"key":"ref23","first-page":"416","article-title":"Staged memory scheduling achieving high performance and scalability in heterogeneous systems","author":"ausavarungnirun","year":"2012","journal-title":"Proc ISCA"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669119"},{"key":"ref25","first-page":"305","article-title":"Predicting multiprocessor memory access patterns with learning models","author":"sakr","year":"1997","journal-title":"Proc ICML"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6862109\/06595566.pdf?arnumber=6595566","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:32:34Z","timestamp":1642005154000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6595566\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,8]]},"references-count":36,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2278025","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,8]]}}}