{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,18]],"date-time":"2026-02-18T22:34:44Z","timestamp":1771454084602,"version":"3.50.1"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2014,9,1]],"date-time":"2014-09-01T00:00:00Z","timestamp":1409529600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/OAPA.html"}],"funder":[{"name":"MODERN, , which is sponsored by the ENIAC consortium and the Italian government"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,9]]},"DOI":"10.1109\/tvlsi.2013.2280295","type":"journal-article","created":{"date-parts":[[2013,9,18]],"date-time":"2013-09-18T14:05:05Z","timestamp":1379513105000},"page":"1990-2003","source":"Crossref","is-referenced-by-count":12,"title":["Multicore Signal Processing Platform With Heterogeneous Configurable Hardware Accelerators"],"prefix":"10.1109","volume":"22","author":[{"given":"Davide","family":"Rossi","sequence":"first","affiliation":[{"name":"Advanced Research Center on Electronic Systems for Information and Communication Technologies, University of Bologna, Bologna, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Claudio","family":"Mucci","sequence":"additional","affiliation":[{"name":"STMicroelectronics, Agrate Brianza, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Matteo","family":"Pizzotti","sequence":"additional","affiliation":[{"name":"STMicroelectronics, Agrate Brianza, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Perugini","sequence":"additional","affiliation":[{"name":"STMicroelectronics, Agrate Brianza, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roberto","family":"Canegallo","sequence":"additional","affiliation":[{"name":"STMicroelectronics, Agrate Brianza, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Roberto","family":"Guerrieri","sequence":"additional","affiliation":[{"name":"Advanced Research Center on Electronic Systems for Information and Communication Technologies, University of Bologna, Bologna, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2006.01.242"},{"key":"ref38","first-page":"33021-1","article-title":"Cost-driven mask strategies considering parametric yield, defectivity, and production volume","volume":"10","author":"jeong","year":"2011","journal-title":"J Micro\/Nanolithogr MEMS MOEMS"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2003.1267720"},{"key":"ref32","year":"0","journal-title":"DesignWare ARC Processor Cores"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.219"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176639"},{"key":"ref37","doi-asserted-by":"crossref","first-page":"142","DOI":"10.1117\/12.485280","article-title":"Cost effective strategies for ASIC masks","volume":"5043","author":"pramanik","year":"2003","journal-title":"Proc SPIE"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2185963"},{"key":"ref35","year":"0","journal-title":"ARM926 Processor"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/212094.212131"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763168"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2180430"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.104"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.886410"},{"key":"ref13","year":"0","journal-title":"Catapult Product Family Overview"},{"key":"ref14","doi-asserted-by":"crossref","first-page":"1523","DOI":"10.1109\/43.898830","article-title":"System-level design: Orthogonalization of concerns and platform-based design","volume":"19","author":"kculzer","year":"2000","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2026356"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.858269"},{"key":"ref17","first-page":"88","article-title":"TILE64 processor: A 64-core SoC with mesh interconnect","author":"bell","year":"2008","journal-title":"Proc IEEE ISSCC"},{"key":"ref18","first-page":"125","article-title":"Parallel processing&#x2014;The picoChip way!","author":"duller","year":"2003","journal-title":"Prco Commun Process Archit"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2170712"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2048594"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.923415"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSOC.2004.1411133"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2091196"},{"key":"ref6","author":"pacheco","year":"1997","journal-title":"Parallel Programming with MPI"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311270"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/99.660313"},{"key":"ref8","year":"2011","journal-title":"OpenCL&#x2014;The Open Standard for Parallel Programming of Heterogeneous Systems"},{"key":"ref7","year":"2011","journal-title":"Nvidia Cuda C Programming Guide v4 0"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"1277","DOI":"10.1109\/TCSI.2010.2096117","article-title":"A low-cost VLSI architecture for robust distributed estimation in wireless sensor networks","volume":"58","author":"chen","year":"2011","journal-title":"IEEE Trans Circuits Syst I Reg Papers"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2012.23"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1117\/12.793067"},{"key":"ref46","year":"0","journal-title":"Embedded Graphics Processors"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2076841"},{"key":"ref45","year":"0","journal-title":"Zynq-7000 All Programmable SoC"},{"key":"ref22","year":"0"},{"key":"ref21","year":"0","journal-title":"SPEAr 32-bit eMPUs"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2004.1339538"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048149"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2006.873163"},{"key":"ref23","year":"0"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1155\/2007\/85318"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/SAMOS.2012.6404162"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ICED.2008.4786751"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815968"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6881768\/06603356.pdf?arnumber=6603356","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,18]],"date-time":"2026-02-18T21:26:10Z","timestamp":1771449970000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6603356\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9]]},"references-count":46,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2280295","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,9]]}}}