{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:12Z","timestamp":1740133272917,"version":"3.37.3"},"reference-count":69,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2014,10,1]],"date-time":"2014-10-01T00:00:00Z","timestamp":1412121600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100000038","name":"NSERC","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Altera"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,10]]},"DOI":"10.1109\/tvlsi.2013.2284281","type":"journal-article","created":{"date-parts":[[2013,11,19]],"date-time":"2013-11-19T18:53:11Z","timestamp":1384887191000},"page":"2067-2080","source":"Crossref","is-referenced-by-count":10,"title":["Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design"],"prefix":"10.1109","volume":"22","author":[{"given":"Henry","family":"Wong","sequence":"first","affiliation":[]},{"given":"Vaughn","family":"Betz","sequence":"additional","affiliation":[]},{"given":"Jonathan","family":"Rose","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","first-page":"3006","article-title":"Tertiary-tree 12-GHz 32-bit adder in 65 nm technology","author":"agah","year":"2007","journal-title":"Proc IEEE ISCAS"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2005.1496692"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.30"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1147\/rd.516.0747"},{"key":"ref31","first-page":"453","article-title":"Self-referenced sense amplifier for across-chipvariation immune sensing in high-performance content-addressable memories","author":"arsovski","year":"2006","journal-title":"Proc IEEE CICC"},{"journal-title":"Using Virtex-II block RAM for high performance read\/write CAMs","year":"2002","author":"brelet","key":"ref30"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ICICDT.2005.1502577"},{"key":"ref36","first-page":"374","article-title":"An 8 GHz floating-point multiply","volume":"1","author":"belluomini","year":"2005","journal-title":"Proc IEEE ISSCC"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859893"},{"key":"ref34","first-page":"303","article-title":"A dual-supply 4 GHz 13fJ\/bit\/search 64 $\\,\\times\\,$ 128 b CAM in 65 nm CMOS","author":"agarwal","year":"2006","journal-title":"Proc 32nd ESSCIRC"},{"key":"ref60","first-page":"9","article-title":"Intel's P6 uses decoupled superscalar design","volume":"9","author":"gwennap","year":"1995","journal-title":"Microprocessor Rep"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/40.491460"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/4.799851"},{"key":"ref63","doi-asserted-by":"publisher","DOI":"10.1109\/4.962281"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864128"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1147\/rd.491.0167"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723122"},{"key":"ref65","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2004.1289290"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.2"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/AICT-ICIW.2006.96"},{"key":"ref67","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746228"},{"key":"ref68","doi-asserted-by":"publisher","DOI":"10.1145\/1152154.1152193"},{"key":"ref69","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598112"},{"journal-title":"Nios II Processor","year":"2011","key":"ref2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950419"},{"key":"ref20","first-page":"2564","article-title":"A 5.6 GHz 64 kB dual-read data cache for the POWER6 processor","author":"davis","year":"2006","journal-title":"Proc IEEE ISSCC"},{"key":"ref22","first-page":"657","article-title":"A 65-nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 $\\mu{\\rm m}^{2}$ SRAM cell","author":"bai","year":"2004","journal-title":"Proc IEEE IEDM"},{"key":"ref21","first-page":"2572","article-title":"A 4.2 GHz 0.3 ${\\rm mm}^{2}$ 256 kB dual-Vcc SRAM building block in 65-nm CMOS","author":"khellah","year":"2006","journal-title":"Proc IEEE ISSCC"},{"key":"ref24","first-page":"252","article-title":"A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65-nm CMOS","author":"chang","year":"2007","journal-title":"Proc VLSI Symp"},{"key":"ref23","article-title":"Foils from 'a 65-nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 $\\mu{\\rm m}^{2}$ SRAM cell'","author":"bai","year":"2004","journal-title":"Proc IEEE IEDM"},{"journal-title":"CACTI 5 1","year":"2008","author":"thoziyoor","key":"ref26"},{"key":"ref25","first-page":"1785","article-title":"An 8.8 GHz 198 mW 16 $\\,\\times\\,$ 64 b 1R\/1W variation-tolerant register file in 65-nm CMOS","author":"hsu","year":"2006","journal-title":"Proc IEEE ISSCC"},{"journal-title":"International Technology Roadmap for Semiconductors","year":"2007","key":"ref50"},{"journal-title":"External Memory Interface Handbook Volume 3","year":"2011","key":"ref51"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/12.48865"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/12.4607"},{"key":"ref57","first-page":"1","article-title":"Highly-associative caches for low-power processors","author":"zhang","year":"2000","journal-title":"Proc 33rd Int Symp Microarchit Appears Kool Chips Workshop"},{"journal-title":"Mini-graph processing","year":"2008","author":"bracy","key":"ref56"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2004.16"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/12.272427"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/144965.145794"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1145\/1086297.1086325"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1508128.1508160"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1216919.1216927"},{"key":"ref40","first-page":"1735","article-title":"A 240 ps 64b carry-lookahead adder in 90 nm CMOS","author":"kao","year":"2006","journal-title":"Proc IEEE ISSCC"},{"key":"ref12","first-page":"245","article-title":"An advanced low power, high performance, strained channel 65 nm technology","author":"tyagi","year":"2005","journal-title":"Proc IEEE IEDM"},{"key":"ref13","first-page":"247","article-title":"A 45-nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging","author":"mistry","year":"2007","journal-title":"Proc IEEE IEDM"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885049"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.910967"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007170"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723116"},{"key":"ref18","first-page":"58","article-title":"A family of 45 nm IA processors","author":"kumar","year":"2009","journal-title":"Proc IEEE ISSCC"},{"journal-title":"OpenSPARC","year":"2010","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884574"},{"journal-title":"MicroBlaze Soft Processor","year":"2004","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/384286.264201"},{"journal-title":"Closing the Gap Between ASIC & Custom Tools and Techniques for High-Performance ASIC Design","year":"2002","author":"chinnery","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065692"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"248","DOI":"10.1145\/342001.339691","article-title":"Clock rate versus IPC: The end of the road for conventional microarchitectures","volume":"28","author":"agarwal","year":"2000","journal-title":"SIGARCH Comp Archit News"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2002.1003558"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/968280.968291"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046195"},{"journal-title":"Stratix II Device Handbook Volume 1","year":"2009","key":"ref45"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1145\/545214.545217"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1145\/545214.545219"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-008-0325-0"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.885055"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.892220"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS.2007.4487969"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6908070\/06663714.pdf?arnumber=6663714","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:24:13Z","timestamp":1642004653000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6663714"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,10]]},"references-count":69,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2284281","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2014,10]]}}}