{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:40:35Z","timestamp":1758894035482},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2014,11,1]],"date-time":"2014-11-01T00:00:00Z","timestamp":1414800000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"National Research Foundation of Korea funded by the Korean government","award":["2010-0024707"],"award-info":[{"award-number":["2010-0024707"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2014,11]]},"DOI":"10.1109\/tvlsi.2013.2288637","type":"journal-article","created":{"date-parts":[[2013,11,19]],"date-time":"2013-11-19T18:53:11Z","timestamp":1384887191000},"page":"2336-2349","source":"Crossref","is-referenced-by-count":25,"title":["A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction"],"prefix":"10.1109","volume":"22","author":[{"given":"Wooheon","family":"Kang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hyungjun","family":"Cho","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joohwan","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sungho","family":"Kang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1198687"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"91","DOI":"10.1109\/ETS.2007.10","article-title":"An integrated built-in test and repair approach for memories with 2-D redundancy","author":"\u00f6hler","year":"2007","journal-title":"Proc IEEE Eur Test Symp"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2005988"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.10.0210.0032"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2044846"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2062830"},{"key":"ref16","first-page":"353","article-title":"An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy","author":"lee","year":"2009","journal-title":"Proc Int SoC Design Conf"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2181510"},{"key":"ref18","first-page":"355","article-title":"Efficient BISR techniques for word-oriented embedded memories with hierarchical redundancy","author":"lu","year":"2006","journal-title":"IEEE\/ACIS ICIS-COMSAR"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2106812"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894250"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/OLT.2002.1030229"},{"key":"ref3","first-page":"175","article-title":"Defect analysis system speeds test and repair of redundant memories","volume":"57","author":"tarr","year":"1984","journal-title":"Electronics"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2007.28"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2003.821925"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"742","DOI":"10.1109\/TVLSI.2005.848824","article-title":"A built-in self-repair design for RAMs with 2-D redundancy","volume":"13","author":"li","year":"2005","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"ref7","first-page":"53","article-title":"A built-in redundancy-analysis scheme for RAMs with 2-D redundancy using 1-D local bitmap","author":"tseng","year":"2006","journal-title":"Proc Design Autom Test Eur"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1985.294737"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.10.0210.0097"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1987.295111"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1049\/el:20083611"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2017906"},{"key":"ref21","first-page":"222","article-title":"On the repair of redundant RAM's","volume":"69","author":"wey","year":"1987","journal-title":"IEEE Trans Comput -Aided Design Integr Circuits Syst"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.864128"},{"key":"ref23","first-page":"234","article-title":"A memory failure pattern analyzer for memory diagnosis and repair","author":"lin","year":"2012","journal-title":"Proc IEEE 30th VLSI Test Symp"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1147\/rd.243.0398"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1975.1050655"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/6932540\/06663698.pdf?arnumber=6663698","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:24:28Z","timestamp":1642004668000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6663698"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,11]]},"references-count":27,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2013.2288637","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,11]]}}}